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| author | Zhi Mao <zhi.mao@mediatek.com> | 2017-06-30 14:05:20 +0800 |
|---|---|---|
| committer | Thierry Reding <thierry.reding@gmail.com> | 2017-08-21 10:39:11 +0200 |
| commit | 8bdb65dc8575978214785462870852a56b6a21ac (patch) | |
| tree | fb421e982b77d6e0afae2e3fc8f7217e4af4093c /drivers/pwm | |
| parent | 62843a6152e7c19f28c368bb51cac1bbfcdf4249 (diff) | |
| download | talos-obmc-linux-8bdb65dc8575978214785462870852a56b6a21ac.tar.gz talos-obmc-linux-8bdb65dc8575978214785462870852a56b6a21ac.zip | |
pwm: mediatek: Disable clock on PWM configuration failure
Make sure to disable the PWM clock if the PWM cannot be configured due
to the clock divider exceeding the maximum value.
While at it, replace the hardcoded maximum clock divider with a defined
constant to improve code readability.
Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
Acked-by: John Crispin <john@phrozen.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Diffstat (limited to 'drivers/pwm')
| -rw-r--r-- | drivers/pwm/pwm-mediatek.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index 637045998318..b52f3afb2ba1 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -30,6 +30,8 @@ #define PWMDWIDTH 0x2c #define PWMTHRES 0x30 +#define PWM_CLK_DIV_MAX 7 + enum { MTK_CLK_MAIN = 0, MTK_CLK_TOP, @@ -130,8 +132,11 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, clkdiv++; } - if (clkdiv > 7) + if (clkdiv > PWM_CLK_DIV_MAX) { + mtk_pwm_clk_disable(chip, pwm); + dev_err(chip->dev, "period %d not supported\n", period_ns); return -EINVAL; + } mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution); |
