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authorHariprasad Shenai <hariprasad@chelsio.com>2014-06-06 21:40:42 +0530
committerDavid S. Miller <davem@davemloft.net>2014-06-10 22:49:54 -0700
commitcf38be6d61001b234d5b980d6e98702587638190 (patch)
tree97f370cf0284a42bcea1abf271487c5807cd7d24 /drivers/net/ethernet/chelsio/cxgb4/t4_msg.h
parentf8c1b7ce00254a5bb75d5b5e5ef1601326a0e08e (diff)
downloadtalos-obmc-linux-cf38be6d61001b234d5b980d6e98702587638190.tar.gz
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iw_cxgb4: Allocate and use IQs specifically for indirect interrupts
Currently indirect interrupts for RDMA CQs funnel through the LLD's RDMA RXQs, which also handle direct interrupts for offload CPLs during RDMA connection setup/teardown. The intended T4 usage model, however, is to have indirect interrupts flow through dedicated IQs. IE not to mix indirect interrupts with CPL messages in an IQ. This patch adds the concept of RDMA concentrator IQs, or CIQs, setup and maintained by the LLD and exported to iw_cxgb4 for use when creating CQs. RDMA CPLs will flow through the LLD's RDMA RXQs, and CQ interrupts flow through the CIQs. Design: cxgb4 creates and exports an array of CIQs for the RDMA ULD. These IQs are sized according to the max available CQs available at adapter init. In addition, these IQs don't need FL buffers since they only service indirect interrupts. One CIQ is setup per RX channel similar to the RDMA RXQs. iw_cxgb4 will utilize these CIQs based on the vector value passed into create_cq(). The num_comp_vectors advertised by iw_cxgb4 will be the number of CIQs configured, and thus the vector value will be the index into the array of CIQs. Based on original work by Steve Wise <swise@opengridcomputing.com> Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/chelsio/cxgb4/t4_msg.h')
0 files changed, 0 insertions, 0 deletions
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