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| author | Josef Ahmad <josef.ahmad@linux.intel.com> | 2013-04-19 17:28:10 +0100 |
|---|---|---|
| committer | Wolfram Sang <wsa@the-dreams.de> | 2013-05-17 10:33:11 +0200 |
| commit | e6f34cea56f5b95498070eaa9f4aa3ba4a9e4f62 (patch) | |
| tree | e3b50a4ea7df97b564811788585759b2ae410dec /drivers/i2c/busses/i2c-designware-core.h | |
| parent | f722406faae2d073cc1d01063d1123c35425939e (diff) | |
| download | talos-obmc-linux-e6f34cea56f5b95498070eaa9f4aa3ba4a9e4f62.tar.gz talos-obmc-linux-e6f34cea56f5b95498070eaa9f4aa3ba4a9e4f62.zip | |
i2c: designware: fix RX FIFO overrun
i2c_dw_xfer_msg() pushes a number of bytes to transmit/receive
to/from the bus into the TX FIFO.
For master-rx transactions, the maximum amount of data that can be
received is calculated depending solely on TX and RX FIFO load.
This is racy - TX FIFO may contain master-rx data yet to be
processed, which will eventually land into the RX FIFO. This
data is not taken into account and the function may request more
data than the controller is actually capable of storing.
This patch ensures the driver takes into account the outstanding
master-rx data in TX FIFO to prevent RX FIFO overrun.
Signed-off-by: Josef Ahmad <josef.ahmad@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Cc: stable@kernel.org
Diffstat (limited to 'drivers/i2c/busses/i2c-designware-core.h')
| -rw-r--r-- | drivers/i2c/busses/i2c-designware-core.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h index 9c1840ee09c7..e761ad18dd61 100644 --- a/drivers/i2c/busses/i2c-designware-core.h +++ b/drivers/i2c/busses/i2c-designware-core.h @@ -60,6 +60,7 @@ * @adapter: i2c subsystem adapter node * @tx_fifo_depth: depth of the hardware tx fifo * @rx_fifo_depth: depth of the hardware rx fifo + * @rx_outstanding: current master-rx elements in tx fifo */ struct dw_i2c_dev { struct device *dev; @@ -88,6 +89,7 @@ struct dw_i2c_dev { u32 master_cfg; unsigned int tx_fifo_depth; unsigned int rx_fifo_depth; + int rx_outstanding; }; #define ACCESS_SWAP 0x00000001 |
