diff options
| author | Damien Lespiau <damien.lespiau@intel.com> | 2015-02-09 19:33:10 +0000 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-02-13 23:28:33 +0100 |
| commit | 9253c2e56b83dcc194f1e47bfd7b2bc1cc09a53f (patch) | |
| tree | 787b4b2deaadf14d04fba4022ef4d1e435572517 /drivers/gpu/drm | |
| parent | 45db2194ac7c91a96b18be32c6d7f12a8695868a (diff) | |
| download | talos-obmc-linux-9253c2e56b83dcc194f1e47bfd7b2bc1cc09a53f.tar.gz talos-obmc-linux-9253c2e56b83dcc194f1e47bfd7b2bc1cc09a53f.zip | |
drm/i915/skl: Implement WaSetGAPSunitClckGateDisable
Let's also take the opportunity the remove the comment telling it's a
pre-prod W/A, it should be obvious from the stepping test.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 3 |
2 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5de6cf450e1a..b00d323095af 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6018,6 +6018,7 @@ enum skl_disp_power_wells { #define GEN6_RSTCTL 0x9420 #define GEN8_UCGCTL6 0x9430 +#define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24) #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14) #define GEN6_GFXPAUSE 0xA000 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b162c5c288bb..af8dca28c505 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -59,9 +59,10 @@ static void skl_init_clock_gating(struct drm_device *dev) if (INTEL_REVID(dev) == SKL_REVID_A0) { /* * WaDisableSDEUnitClockGating:skl - * This seems to be a pre-production w/a. + * WaSetGAPSunitClckGateDisable:skl */ I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | + GEN8_GAPSUNIT_CLOCK_GATE_DISABLE | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); } } |
