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authorStefan Agner <stefan@agner.ch>2016-12-08 14:54:31 -0800
committerThierry Reding <treding@nvidia.com>2017-01-26 10:57:18 +0100
commiteaeebffa90f35e0f92658249b0e5c49ddfa89915 (patch)
treed7fc3a84d0df5003c2bf02b5fe6c415a96758fe3 /drivers/gpu/drm/panel
parente6c2f066d5ed5ba61d48d54b603698bad1c6a270 (diff)
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drm/panel: simple: Specify bus width and flags for EDT displays
The display has a 18-Bit parallel LCD interface, require DE to be active high and data driven by the controller on falling pixel clock edge (display samples on rising edge). Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/panel')
-rw-r--r--drivers/gpu/drm/panel/panel-simple.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index be35f3fa7e9a..89eb0422821c 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -802,6 +802,8 @@ static const struct panel_desc edt_et057090dhu = {
.width = 115,
.height = 86,
},
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
};
static const struct drm_display_mode edt_etm0700g0dh6_mode = {
@@ -826,6 +828,8 @@ static const struct panel_desc edt_etm0700g0dh6 = {
.width = 152,
.height = 91,
},
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
};
static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
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