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| author | Sean Paul <seanpaul@chromium.org> | 2018-09-27 02:54:54 -0400 |
|---|---|---|
| committer | Sean Paul <seanpaul@chromium.org> | 2018-09-27 02:54:54 -0400 |
| commit | 7b76d0588477d4b6097a9048b42835a45caf5c48 (patch) | |
| tree | fa4e0bcd49f8d17f26795224290c8f8460aa4116 /drivers/gpu/drm/i915/intel_i2c.c | |
| parent | a74c0aa524050e5fd6c275a153b1f37283f6e37c (diff) | |
| parent | bf78296ab1cb215d0609ac6cff4e43e941e51265 (diff) | |
| download | talos-obmc-linux-7b76d0588477d4b6097a9048b42835a45caf5c48.tar.gz talos-obmc-linux-7b76d0588477d4b6097a9048b42835a45caf5c48.zip | |
Merge drm/drm-next into drm-misc-next
Backmerging 4.19-rc5 to pick up sun4i fix
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_i2c.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_i2c.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index bef32b7c248e..33d87ab93fdd 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -37,7 +37,7 @@ struct gmbus_pin { const char *name; - i915_reg_t reg; + enum i915_gpio gpio; }; /* Map gmbus pin pairs to names and registers. */ @@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, else size = ARRAY_SIZE(gmbus_pins); - return pin < size && - i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg); + return pin < size && get_gmbus_pin(dev_priv, pin)->name; } /* Intel GPIO access functions */ @@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) algo = &bus->bit_algo; - bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base + - i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg)); + bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio); bus->adapter.algo_data = algo; algo->setsda = set_data; algo->setscl = set_clock; @@ -825,9 +823,11 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv) if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; else if (!HAS_GMCH_DISPLAY(dev_priv)) - dev_priv->gpio_mmio_base = - i915_mmio_reg_offset(PCH_GPIOA) - - i915_mmio_reg_offset(GPIOA); + /* + * Broxton uses the same PCH offsets for South Display Engine, + * even though it doesn't have a PCH. + */ + dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE; mutex_init(&dev_priv->gmbus_mutex); init_waitqueue_head(&dev_priv->gmbus_wait_queue); |
