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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-10-29 21:25:53 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-11-10 16:23:06 +0200 |
| commit | d2d65408cc8a2368e86bda934f6feafd355e5299 (patch) | |
| tree | 5e2925f4f2b8b889902c82ed97354e1fad0c6746 /drivers/gpu/drm/i915/intel_fbc.c | |
| parent | 37ca8d4ccd9860df0747aa2ea281a3c9c4bf8826 (diff) | |
| download | talos-obmc-linux-d2d65408cc8a2368e86bda934f6feafd355e5299.tar.gz talos-obmc-linux-d2d65408cc8a2368e86bda934f6feafd355e5299.zip | |
drm/i915: Enable PCH FIFO underruns later on HSW+
As we did for ILK/SNB/IVB, move the PCH FIFO underrun enable to happen
after the encoder enable on HSW+. And again, for symmetry, move the
the disable to happen before encoder disable.
I've left out the vblank wait before the enable here because I don't
know if it's needed or not. Actually I don't know if this entire
change is needed as I don't have a HSW/BDW with VGA output.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446146763-31821-5-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_fbc.c')
0 files changed, 0 insertions, 0 deletions
