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author | Chris Wilson <chris@chris-wilson.co.uk> | 2017-03-09 21:12:30 +0000 |
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committer | Chris Wilson <chris@chris-wilson.co.uk> | 2017-03-10 14:28:39 +0000 |
commit | e0e8c7cb6eb68e9256de2d8cbeb481d3701c05ac (patch) | |
tree | 8f66b1f4c6b056f0268b2e37105f26c935966494 /drivers/gpu/drm/i915/i915_drv.h | |
parent | 8eadc19b380d5650e9d9c58e8ecc28e9f2b4a371 (diff) | |
download | talos-obmc-linux-e0e8c7cb6eb68e9256de2d8cbeb481d3701c05ac.tar.gz talos-obmc-linux-e0e8c7cb6eb68e9256de2d8cbeb481d3701c05ac.zip |
drm/i915: Stop using RP_DOWN_EI on Baytrail
On Baytrail, we manually calculate busyness over the evaluation interval
to avoid issues with miscaluations with RC6 enabled. However, it turns
out that the DOWN_EI interrupt generator is completely bust - it
operates in two modes, continuous or never. Neither of which are
conducive to good behaviour. Stop unmask the DOWN_EI interrupt and just
compute everything from the UP_EI which does seem to correspond to the
desired interval.
v2: Fixup gen6_rps_pm_mask() as well
v3: Inline vlv_c0_above() to combine the now identical elapsed
calculation for up/down and simplify the threshold testing
Fixes: 43cf3bf084ba ("drm/i915: Improved w/a for rps on Baytrail")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: <stable@vger.kernel.org> # v4.1+
Link: http://patchwork.freedesktop.org/patch/msgid/20170309211232.28878-1-chris@chris-wilson.co.uk
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b02eb362b890..4d1fb620de8f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1376,7 +1376,7 @@ struct intel_gen6_power_mgmt { unsigned boosts; /* manual wa residency calculations */ - struct intel_rps_ei up_ei, down_ei; + struct intel_rps_ei ei; /* * Protects RPS/RC6 register access and PCU communication. |