diff options
| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2018-02-22 12:05:35 -0800 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2018-02-27 15:54:30 -0800 |
| commit | d66047e4a582103d4c6a884692f402b905032f26 (patch) | |
| tree | 89833a5f480102076e7b52770a5846da07313687 /drivers/gpu/drm/i915/i915_drv.h | |
| parent | c4932d7956d8226e20c0c44b04fe9a2cbfcd8f51 (diff) | |
| download | talos-obmc-linux-d66047e4a582103d4c6a884692f402b905032f26.tar.gz talos-obmc-linux-d66047e4a582103d4c6a884692f402b905032f26.zip | |
drm/i915/cnl: Add WaRsDisableCoarsePowerGating
Old Wa added now forever on CNL all steppings.
With CPU P states enabled along with RC6, dispatcher
hangs can happen.
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180222200535.9290-1-rodrigo.vivi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9143d0d6be5a..2711149189f1 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2788,9 +2788,10 @@ intel_info(const struct drm_i915_private *dev_priv) /* Early gen2 have a totally busted CS tlb and require pinned batches. */ #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) -/* WaRsDisableCoarsePowerGating:skl,bxt */ +/* WaRsDisableCoarsePowerGating:skl,cnl */ #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ - (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv)) + (IS_CANNONLAKE(dev_priv) || \ + IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv)) /* * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts |
