diff options
| author | Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> | 2014-10-29 11:32:32 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-11-07 18:41:43 +0100 |
| commit | 3e369b76ceb625dffabef6f1c52e32fc0998843e (patch) | |
| tree | 57a2a973fd4b5f86c7addb25ffe257ead5c94b77 /drivers/gpu/drm/i915/i915_debugfs.c | |
| parent | 1e6f2ddc88fec990ef4fb1aa3b7cb9941df0321b (diff) | |
| download | talos-obmc-linux-3e369b76ceb625dffabef6f1c52e32fc0998843e.tar.gz talos-obmc-linux-3e369b76ceb625dffabef6f1c52e32fc0998843e.zip | |
drm/i915: Move dpll crtc_mask and hw_state fields into separate struct
The new struct will be used in a follow up patch to allow a current and
a staged config to exist for the same shared DPLL.
v2: Rebase on by mask_to_refcount()->hweight32() change. (Damien)
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_debugfs.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_debugfs.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index ce32ae788c3c..0a6981399642 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2631,13 +2631,14 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused) seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n", - pll->crtc_mask, pll->active, yesno(pll->on)); + pll->config.crtc_mask, pll->active, yesno(pll->on)); seq_printf(m, " tracked hardware state:\n"); - seq_printf(m, " dpll: 0x%08x\n", pll->hw_state.dpll); - seq_printf(m, " dpll_md: 0x%08x\n", pll->hw_state.dpll_md); - seq_printf(m, " fp0: 0x%08x\n", pll->hw_state.fp0); - seq_printf(m, " fp1: 0x%08x\n", pll->hw_state.fp1); - seq_printf(m, " wrpll: 0x%08x\n", pll->hw_state.wrpll); + seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); + seq_printf(m, " dpll_md: 0x%08x\n", + pll->config.hw_state.dpll_md); + seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); + seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); + seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); } drm_modeset_unlock_all(dev); |
