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| author | Charlene Liu <charlene.liu@amd.com> | 2018-06-18 19:50:07 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-07-13 14:48:10 -0500 |
| commit | 8e8539c2fcdf65b6a2e6ceb93e56034896e47dd0 (patch) | |
| tree | 135edaec83684e3466596811b6227ec8b51aba75 /drivers/gpu/drm/amd/display/dc/dce | |
| parent | 0252c9425f20ade8bfcb5ad4f1e150940acbe39c (diff) | |
| download | talos-obmc-linux-8e8539c2fcdf65b6a2e6ceb93e56034896e47dd0.tar.gz talos-obmc-linux-8e8539c2fcdf65b6a2e6ceb93e56034896e47dd0.zip | |
drm/amd/display: Define couple extra DCN registers
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index f091d87f8f8b..df3203a1d278 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -147,6 +147,7 @@ SR(DCCG_GATE_DISABLE_CNTL2), \ SR(DCFCLK_CNTL),\ SR(DCFCLK_CNTL), \ + SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ /* todo: get these from GVM instead of reading registers ourselves */\ MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\ MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\ |
