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authorArnd Bergmann <arnd@arndb.de>2017-02-16 17:46:52 +0100
committerArnd Bergmann <arnd@arndb.de>2017-02-16 17:46:52 +0100
commitd0f7de9258e1fa7b531f10a6bdb971a2417dfd8a (patch)
tree2fc19fb337ad9f1a17ed0cc7b4fc17f6465aaa17 /drivers/clk
parenta121103c922847ba5010819a3f250f1f7fc84ab8 (diff)
parent6629490aa027a8af3160e63cffcddc97c1602c96 (diff)
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Merge tag 'samsung-dt64-4.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/late
Pull "Samsung DeviceTree ARM64 update for v4.11, third round" from Krzysztof Kozłowski: 1. Add necessary initial configuration for clocks of display subsystem. Till now it worked mostly thanks to bootloader. 2. Use macro definitions instead of hard-coded values for pinctrl on Exynos7. 3. Enable USB 3.0 (DWC3) on Exynos7. * tag 'samsung-dt64-4.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (27 commits) arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost arm64: dts: exynos: Add USB 3.0 controller node for Exynos7 arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7 pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks arm64: dts: exynos: Add clocks to Exynos5433 LPASS module arm64: dts: exynos: set LDO7 regulator as always on arm64: dts: exynos: configure TV path clocks for Ultra HD modes arm64: dts: exynos: Fix drive strength of sd0_xxx pin definitions arm64: dts: exynos: Disable pull down for audio pins in Exynos5433 SoCs arm64: dts: exynos: Add TM2 touchkey node arm64: dts: exynos: Remove unneeded unit names in Exynos5433 nodes arm64: dts: exynos: Enable HDMI/TV path on Exynos5433-TM2 arm64: dts: exynos: Add HDMI node to Exynos5433 arm64: dts: exynos: Add DECON_TV node to Exynos5433 arm64: dts: exynos: Fix addresses in node names on Exynos5433 arm64: dts: exynos: Make TM2 and TM2E independent from each other arm64: dts: exynos: Fix wrong values for ldo23 and ldo25 on TM2/TM2E ...
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/samsung/clk-exynos5433.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index f096bd7df40c..3feaea8be40e 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -739,7 +739,9 @@ static const struct samsung_pll_rate_table exynos5443_pll_rates[] __initconst =
PLL_35XX_RATE(350000000U, 350, 6, 2),
PLL_35XX_RATE(333000000U, 222, 4, 2),
PLL_35XX_RATE(300000000U, 500, 5, 3),
+ PLL_35XX_RATE(278000000U, 556, 6, 3),
PLL_35XX_RATE(266000000U, 532, 6, 3),
+ PLL_35XX_RATE(250000000U, 500, 6, 3),
PLL_35XX_RATE(200000000U, 400, 6, 3),
PLL_35XX_RATE(166000000U, 332, 6, 3),
PLL_35XX_RATE(160000000U, 320, 6, 3),
@@ -2559,8 +2561,10 @@ static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = {
FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
/* PHY clocks from MIPI_DPHY0 */
- FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, 0, 188000000),
- FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, 0, 100000000),
+ FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy",
+ NULL, 0, 188000000),
+ FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy",
+ NULL, 0, 100000000),
/* PHY clocks from HDMI_PHY */
FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
NULL, 0, 300000000),
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