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author | Stephen Boyd <sboyd@codeaurora.org> | 2016-09-14 11:06:47 -0700 |
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committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-09-14 11:06:47 -0700 |
commit | 3db385ea144daea9c6e1a15f98eacafaec9ad9f1 (patch) | |
tree | 25316f2cb4f42674bcd127d3b812e17cbfe536eb /drivers/clk/sunxi-ng/ccu_nm.c | |
parent | 7348b6ce94019548f64d54c6934d5ace3f2b50a9 (diff) | |
parent | be95d2c7d918b2b7b973378a1e92bdc6559c21f9 (diff) | |
download | talos-obmc-linux-3db385ea144daea9c6e1a15f98eacafaec9ad9f1.tar.gz talos-obmc-linux-3db385ea144daea9c6e1a15f98eacafaec9ad9f1.zip |
Merge tag 'clk-v4.9-samsung' of git://linuxtv.org/snawrocki/samsung into clk-next
Pull samsung clk driver updates from Sylwester Nawrocki:
In addition to a few clean up and code consolidation patches this
includes:
- addition of sound subsystem related clocks for Exynos5410 SoC
(EPLL, PDMA) and support for "samsung,exynos5410-audss-clock"
compatible in the clk-exynos-audss driver,
- addition of DRAM controller related clocks for exynos5420,
- MAINTAINERS update adding Chanwoo Choi as the Samsung SoC
clock drivers co-maintainer.
* tag 'clk-v4.9-samsung' of git://linuxtv.org/snawrocki/samsung:
clk: samsung: Add support for EPLL on exynos5410
clk: samsung: clk-exynos-audss: Whitespace and debug trace cleanup
clk: samsung: clk-exynos-audss: Add exynos5410 compatible
clk: samsung: clk-exynos-audss: controller variant handling rework
clk: samsung: Use common registration function for pll2550x
clk: samsung: exynos5410: Expose the peripheral DMA gate clocks
clk: samsung: exynos5420: Add clocks for CMU_CDREX domain
clk: samsung: exynos5410: Use samsung_cmu_register_one() to simplify code
clk: samsung: exynos5260: Move struct samsung_cmu_info to init section
MAINTAINERS: Add myself as Samsung SoC clock drivers co-maintainer
clk: samsung: exynos5410: Add clock IDs for PDMA and EPLL clocks
clk: samsung: Add clock IDs for the CMU_CDREX (DRAM Express Controller)
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu_nm.c')
0 files changed, 0 insertions, 0 deletions