diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-02-28 17:31:59 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-03-21 11:12:07 +0100 |
| commit | a843ed3f6c3e856f9091b042c6b4ed34c02a3187 (patch) | |
| tree | 7b7b0817c3d5143aff696a3c11fad97b645a5cb6 /drivers/clk/renesas | |
| parent | 6c8a9312946374947287ac1bd3b94aba850a5d1f (diff) | |
| download | talos-obmc-linux-a843ed3f6c3e856f9091b042c6b4ed34c02a3187.tar.gz talos-obmc-linux-a843ed3f6c3e856f9091b042c6b4ed34c02a3187.zip | |
clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs
The parent clock of the Audio DMACs is the "ZS" AXI bus clock, which
maps to S3D1 on R-Car H3 ES1.x.
All module clocks must be sorted by clock ID.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index 2add8218e0f7..cde470ce81e4 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -142,8 +142,8 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { DEF_MOD("rwdt0", 402, R8A7795_CLK_R), DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), - DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4), - DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4), + DEF_MOD("audmac1", 501, R8A7795_CLK_S3D1), + DEF_MOD("audmac0", 502, R8A7795_CLK_S3D1), DEF_MOD("drif7", 508, R8A7795_CLK_S3D2), DEF_MOD("drif6", 509, R8A7795_CLK_S3D2), DEF_MOD("drif5", 510, R8A7795_CLK_S3D2), |
