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| author | Jerome Brunet <jbrunet@baylibre.com> | 2018-02-12 15:58:43 +0100 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2018-03-13 10:04:03 +0100 |
| commit | d610b54f77002bbddca54c10d9488c2faa7ff102 (patch) | |
| tree | a991e55607dc05c8f35690122bb66dad30ae55ec /drivers/clk/meson/meson8b.h | |
| parent | 722825dcd54b2e427c1aee54a7992eb4ab04a49d (diff) | |
| download | talos-obmc-linux-d610b54f77002bbddca54c10d9488c2faa7ff102.tar.gz talos-obmc-linux-d610b54f77002bbddca54c10d9488c2faa7ff102.zip | |
clk: meson: split divider and gate part of mpll
The mpll clock is a kind of fractional divider which can gate.
When the RW operation have been added, enable/disable ops have been
mistakenly inserted in this driver. These ops are essentially a
poor copy/paste of the generic gate ops.
This change removes the gate ops from the mpll driver and inserts a
generic gate clock on each mpll divider, simplifying the mpll
driver and reducing code duplication.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/meson8b.h')
| -rw-r--r-- | drivers/clk/meson/meson8b.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index 2eaf8a52e7dd..f2780508edec 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -69,7 +69,11 @@ * will remain defined here. */ -#define CLK_NR_CLKS 96 +#define CLKID_MPLL0_DIV 96 +#define CLKID_MPLL1_DIV 97 +#define CLKID_MPLL2_DIV 98 + +#define CLK_NR_CLKS 99 /* * include the CLKID and RESETID that have |
