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| author | Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> | 2011-12-04 16:07:47 +0100 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2011-12-08 18:02:28 -0800 |
| commit | c116abc43df9ce3ebe5fbf2fbd6ae2edd6a9bd87 (patch) | |
| tree | 192d5179faf468851e1782273a788d275e0c8213 /arch | |
| parent | f9e5908fa04e15a681dc4695b53c2c0c1d9b9a03 (diff) | |
| download | talos-obmc-linux-c116abc43df9ce3ebe5fbf2fbd6ae2edd6a9bd87.tar.gz talos-obmc-linux-c116abc43df9ce3ebe5fbf2fbd6ae2edd6a9bd87.zip | |
ARM: OMAP1: Always reprogram dpll1 rate at boot
DPLL1 reprogramming to a different rate is actually blocked inside
omap1_select_table_rate(). However, it is already forced at boot, for
boards which boot at unusable clock rates, and this seems to work
correctly.
OTOH, we now have a fine, run time performed clock selection algorithm
implemented, which prevents less powerfull SoCs from being overclocked
unintentionally.
Allow reprogramming of dpll1 by default, and use it for switching to the
higest supported clock rate with all boards, including those already
booting at a usable rate of 60 MHz or above.
Created against linux-omap/master tip as of Thu Dec 1,
commit f83c2a8cbb59981722d1ab610c79adfd034a2667. Requires the just
submitted patch "ARM: OMAP1: Move dpll1 rates selection from config to
runtime" to prevent from unintentional overclocking. Tested on Amstrad
Delta.
Signed-off-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-omap1/clock.c | 4 | ||||
| -rw-r--r-- | arch/arm/mach-omap1/clock_data.c | 6 |
2 files changed, 0 insertions, 10 deletions
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 6d8f7c640237..0c50df05d135 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -203,10 +203,6 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate) if (ptr->xtal != ref_rate) continue; - /* DPLL1 cannot be reprogrammed without risking system crash */ - if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate) - continue; - /* Can check only after xtal frequency check */ if (ptr->rate <= rate) break; diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index 9d1a42a5afd8..94699a82a734 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -936,12 +936,6 @@ void __init omap1_clk_late_init(void) { unsigned long rate = ck_dpll1.rate; - if (rate >= OMAP1_DPLL1_SANE_VALUE) - return; - - /* System booting at unusable rate, force reprogramming of DPLL1 */ - ck_dpll1_p->rate = 0; - /* Find the highest supported frequency and enable it */ if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { pr_err("System frequencies not set, using default. Check your config.\n"); |
