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| author | Xiao Guangrong <guangrong.xiao@linux.intel.com> | 2015-09-09 14:05:51 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2015-10-01 15:06:35 +0200 |
| commit | 8b3e34e46aca9b6d349b331cd9cf71ccbdc91b2e (patch) | |
| tree | e908c0be3a3ea4649fc767df6ad03306e9116edf /arch/x86/include/asm/vmx.h | |
| parent | eb1c31b46800a476644cd63ab3bc7ef918b0a917 (diff) | |
| download | talos-obmc-linux-8b3e34e46aca9b6d349b331cd9cf71ccbdc91b2e.tar.gz talos-obmc-linux-8b3e34e46aca9b6d349b331cd9cf71ccbdc91b2e.zip | |
KVM: x86: add pcommit support
Pass PCOMMIT CPU feature to guest to enable PCOMMIT instruction
Currently we do not catch pcommit instruction for L1 guest and
allow L1 to catch this instruction for L2 if, as required by the spec,
L1 can enumerate the PCOMMIT instruction via CPUID:
| IA32_VMX_PROCBASED_CTLS2[53] (which enumerates support for the
| 1-setting of PCOMMIT exiting) is always the same as
| CPUID.07H:EBX.PCOMMIT[bit 22]. Thus, software can set PCOMMIT exiting
| to 1 if and only if the PCOMMIT instruction is enumerated via CPUID
The spec can be found at
https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/x86/include/asm/vmx.h')
| -rw-r--r-- | arch/x86/include/asm/vmx.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h index 448b7ca61aee..d25f32ac9c5c 100644 --- a/arch/x86/include/asm/vmx.h +++ b/arch/x86/include/asm/vmx.h @@ -72,7 +72,7 @@ #define SECONDARY_EXEC_SHADOW_VMCS 0x00004000 #define SECONDARY_EXEC_ENABLE_PML 0x00020000 #define SECONDARY_EXEC_XSAVES 0x00100000 - +#define SECONDARY_EXEC_PCOMMIT 0x00200000 #define PIN_BASED_EXT_INTR_MASK 0x00000001 #define PIN_BASED_NMI_EXITING 0x00000008 |
