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author | Paul Mundt <lethal@linux-sh.org> | 2010-12-01 15:39:51 +0900 |
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committer | Paul Mundt <lethal@linux-sh.org> | 2010-12-01 15:39:51 +0900 |
commit | 55661fc1f105ed75852e937bf8ea408270eb0cca (patch) | |
tree | aa96c0c6dd0a8230f9373cab32cd069564d27d23 /arch/sh/include | |
parent | 22a5b566c8c442b0b35b3b106795e2f2b3578096 (diff) | |
download | talos-obmc-linux-55661fc1f105ed75852e937bf8ea408270eb0cca.tar.gz talos-obmc-linux-55661fc1f105ed75852e937bf8ea408270eb0cca.zip |
sh: Assume new page cache pages have dirty dcache lines.
This follows the ARM change c01778001a4f5ad9c62d882776235f3f31922fdd
("ARM: 6379/1: Assume new page cache pages have dirty D-cache") for the
same rationale:
There are places in Linux where writes to newly allocated page
cache pages happen without a subsequent call to flush_dcache_page()
(several PIO drivers including USB HCD). This patch changes the
meaning of PG_arch_1 to be PG_dcache_clean and always flush the
D-cache for a newly mapped page in update_mmu_cache().
This addresses issues seen with executing binaries from MMC, in
addition to some of the other HCDs that don't explicitly do cache
management for their pipe-in buffers.
Requested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include')
-rw-r--r-- | arch/sh/include/asm/cacheflush.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/sh/include/asm/cacheflush.h b/arch/sh/include/asm/cacheflush.h index 1f4e562c5e8c..82e1eabeac98 100644 --- a/arch/sh/include/asm/cacheflush.h +++ b/arch/sh/include/asm/cacheflush.h @@ -96,7 +96,7 @@ void kmap_coherent_init(void); void *kmap_coherent(struct page *page, unsigned long addr); void kunmap_coherent(void *kvaddr); -#define PG_dcache_dirty PG_arch_1 +#define PG_dcache_clean PG_arch_1 void cpu_cache_init(void); |