diff options
author | Matthias Fuchs <matthias.fuchs@esd-electronics.com> | 2006-06-14 15:35:05 +0200 |
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committer | Paul Mackerras <paulus@samba.org> | 2006-06-15 19:31:27 +1000 |
commit | 2ba73b1d6fa62ddaa235c3c5fdf6095cae6ba748 (patch) | |
tree | cd1d84913a99e685fbc2a6a088ca86afc7d25501 /arch/ppc/platforms/4xx/cpci405.h | |
parent | 4312dc76a88146c4f1d693fc4643d1df12aaf755 (diff) | |
download | talos-obmc-linux-2ba73b1d6fa62ddaa235c3c5fdf6095cae6ba748.tar.gz talos-obmc-linux-2ba73b1d6fa62ddaa235c3c5fdf6095cae6ba748.zip |
[POWERPC] ppc32: fix CPCI405 board support
Hi,
this patch brings the CPCI405 board support up to date and fixes several
outstanding issues:
-add bios_fixup()
-enable RTC only when CONFIG_GEN_RTC defined
-corrected CompactPCI interrupt map
-added cpci405_early_serial_map for correct UART clocking
-removed unused code
Matthias
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/ppc/platforms/4xx/cpci405.h')
-rw-r--r-- | arch/ppc/platforms/4xx/cpci405.h | 30 |
1 files changed, 11 insertions, 19 deletions
diff --git a/arch/ppc/platforms/4xx/cpci405.h b/arch/ppc/platforms/4xx/cpci405.h index e27f7cb650d8..f5a5c0cd062d 100644 --- a/arch/ppc/platforms/4xx/cpci405.h +++ b/arch/ppc/platforms/4xx/cpci405.h @@ -1,37 +1,29 @@ /* * CPCI-405 board specific definitions * - * Copyright (c) 2001 Stefan Roese (stefan.roese@esd-electronics.com) + * Copyright 2001-2006 esd electronic system design - hannover germany + * + * Authors: Matthias Fuchs + * matthias.fuchs@esd-electronics.com + * Stefan Roese + * stefan.roese@esd-electronics.com */ #ifdef __KERNEL__ -#ifndef __ASM_CPCI405_H__ -#define __ASM_CPCI405_H__ +#ifndef __CPCI405_H__ +#define __CPCI405_H__ #include <linux/config.h> - -/* We have a 405GP core */ #include <platforms/4xx/ibm405gp.h> - #include <asm/ppcboot.h> -#ifndef __ASSEMBLY__ -/* Some 4xx parts use a different timebase frequency from the internal clock. -*/ -#define bi_tbfreq bi_intfreq - /* Map for the NVRAM space */ #define CPCI405_NVRAM_PADDR ((uint)0xf0200000) #define CPCI405_NVRAM_SIZE ((uint)32*1024) -#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK -#define BASE_BAUD 201600 -#else -#define BASE_BAUD 691200 -#endif +#define BASE_BAUD 0 -#define PPC4xx_MACHINE_NAME "esd CPCI-405" +#define PPC4xx_MACHINE_NAME "esd CPCI-405" -#endif /* !__ASSEMBLY__ */ -#endif /* __ASM_CPCI405_H__ */ +#endif /* __CPCI405_H__ */ #endif /* __KERNEL__ */ |