diff options
| author | Madhavan Srinivasan <maddy@linux.vnet.ibm.com> | 2018-06-10 19:57:01 +0530 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2018-12-20 20:53:11 +1100 |
| commit | 59029136d75022cb8b7c7bebd1738ae70232416e (patch) | |
| tree | e6897a355013a5f03a7da87d0ae1bf7b7d2514d9 /arch/powerpc/perf/isa207-common.h | |
| parent | 2d46d4877b1afd14059393a48bdb8ce27955174c (diff) | |
| download | talos-obmc-linux-59029136d75022cb8b7c7bebd1738ae70232416e.tar.gz talos-obmc-linux-59029136d75022cb8b7c7bebd1738ae70232416e.zip | |
powerpc/perf: Add constraints for power9 l2/l3 bus events
In previous generation processors, both bus events and direct
events of performance monitoring unit can be individually
programmabled and monitored in PMCs.
But in Power9, L2/L3 bus events are always available as a
"bank" of 4 events. To obtain the counts for any of the
l2/l3 bus events in a given bank, the user will have to
program PMC4 with corresponding l2/l3 bus event for that
bank.
Patch enforce two contraints incase of L2/L3 bus events.
1)Any L2/L3 event when programmed is also expected to program corresponding
PMC4 event from that group.
2)PMC4 event should always been programmed first due to group constraint
logic limitation
For ex. consider these L3 bus events
PM_L3_PF_ON_CHIP_MEM (0x460A0),
PM_L3_PF_MISS_L3 (0x160A0),
PM_L3_CO_MEM (0x260A0),
PM_L3_PF_ON_CHIP_CACHE (0x360A0),
1) This is an INVALID group for L3 Bus event monitoring,
since it is missing PMC4 event.
perf stat -e "{r160A0,r260A0,r360A0}" < >
And this is a VALID group for L3 Bus events:
perf stat -e "{r460A0,r160A0,r260A0,r360A0}" < >
2) This is an INVALID group for L3 Bus event monitoring,
since it is missing PMC4 event.
perf stat -e "{r260A0,r360A0}" < >
And this is a VALID group for L3 Bus events:
perf stat -e "{r460A0,r260A0,r360A0}" < >
3) This is an INVALID group for L3 Bus event monitoring,
since it is missing PMC4 event.
perf stat -e "{r360A0}" < >
And this is a VALID group for L3 Bus events:
perf stat -e "{r460A0,r360A0}" < >
Patch here implements group constraint logic suggested by Michael Ellerman.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/perf/isa207-common.h')
| -rw-r--r-- | arch/powerpc/perf/isa207-common.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h index e5a621699a6d..91350f42a662 100644 --- a/arch/powerpc/perf/isa207-common.h +++ b/arch/powerpc/perf/isa207-common.h @@ -134,6 +134,11 @@ #define CNST_SAMPLE_VAL(v) (((v) & EVENT_SAMPLE_MASK) << 16) #define CNST_SAMPLE_MASK CNST_SAMPLE_VAL(EVENT_SAMPLE_MASK) +#define CNST_CACHE_GROUP_VAL(v) (((v) & 0xffull) << 55) +#define CNST_CACHE_GROUP_MASK CNST_CACHE_GROUP_VAL(0xff) +#define CNST_CACHE_PMC4_VAL (1ull << 54) +#define CNST_CACHE_PMC4_MASK CNST_CACHE_PMC4_VAL + /* * For NC we are counting up to 4 events. This requires three bits, and we need * the fifth event to overflow and set the 4th bit. To achieve that we bias the |
