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authorJohn Crispin <blogic@openwrt.org>2012-07-22 08:55:57 +0200
committerRalf Baechle <ralf@linux-mips.org>2012-08-01 17:57:04 +0200
commite29b72f5e129b4dd4b77dc01dba340006bb103f8 (patch)
treef0425aa961e2becc0e4454eba8d04832be6eda74 /arch/mips/lantiq/prom.c
parent2e3ee613480563a6d5c01b57d342e65cc58c06df (diff)
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MIPS: Lantiq: Fix interface clock and PCI control register offset
The XRX200 based SoC have a different register offset for the interface clock and PCI control registers. This patch detects the SoC and sets the register offset at runtime. This make PCI work on the VR9 SoC. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4113/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/lantiq/prom.c')
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