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authorMaciej W. Rozycki <macro@linux-mips.org>2014-06-29 00:26:20 +0100
committerRalf Baechle <ralf@linux-mips.org>2014-07-30 15:51:55 +0200
commitdb873131487acf9bf87d42f26e283c8087b70e7e (patch)
tree907cb94ac173dc6f543666d9535d27e3c170281c /arch/mips/include
parentbf4aac07b5cc21517bde0bf132cba5e72955513c (diff)
downloadtalos-obmc-linux-db873131487acf9bf87d42f26e283c8087b70e7e.tar.gz
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MIPS: asm/bitops.h: Guard CLZ with `.set mips32'
This fixes: {standard input}: Assembler messages: {standard input}:145: Error: opcode not supported on this processor: vr5000 (mips4) `clz $2,$2' {standard input}:920: Error: opcode not supported on this processor: vr5000 (mips4) `clz $7,$9' {standard input}:1797: Error: opcode not supported on this processor: vr5000 (mips4) `clz $7,$7' {standard input}:1851: Error: opcode not supported on this processor: vr5000 (mips4) `clz $7,$7' {standard input}:2831: Error: opcode not supported on this processor: vr5000 (mips4) `clz $7,$7' {standard input}:4209: Error: opcode not supported on this processor: vr5000 (mips4) `clz $7,$7' {standard input}:4329: Error: opcode not supported on this processor: vr5000 (mips4) `clz $2,$2' make[2]: *** [arch/mips/mm/tlbex.o] Error 1 which triggered due to a regression causing the file to be built with `-march=r5000' rather than `-march=sb1', fixed separately. Nevertheless the error should not happen, the other uses of CLZ are appropriately guarded. This change copies the arrangement from one of those other places. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7222/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/bitops.h8
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 7c8816f7b7c4..bae6b0fa8ab5 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -559,7 +559,13 @@ static inline int fls(int x)
int r;
if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
- __asm__("clz %0, %1" : "=r" (x) : "r" (x));
+ __asm__(
+ " .set push \n"
+ " .set mips32 \n"
+ " clz %0, %1 \n"
+ " .set pop \n"
+ : "=r" (x)
+ : "r" (x));
return 32 - x;
}
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