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author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-12-19 17:57:51 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-12-19 17:57:51 -0800 |
commit | 5be95b7e24bde4d93ff1bff5911b303043753168 (patch) | |
tree | 00ccba63052e5f9b5adbf13e48f3fdbcab77a48c /arch/hexagon/include/asm/cacheflush.h | |
parent | 971d9e07e18fa3684e7fbc932f01aa2a0682f232 (diff) | |
parent | 8914d7e857807e1e60975000cba3750c9b2643e8 (diff) | |
download | talos-obmc-linux-5be95b7e24bde4d93ff1bff5911b303043753168.tar.gz talos-obmc-linux-5be95b7e24bde4d93ff1bff5911b303043753168.zip |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rkuo/linux-hexagon-kernel
Pull arch/hexagon updates from Richard Kuo:
"Build cleanup and a few misc fixes"
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rkuo/linux-hexagon-kernel:
Hexagon: fix signal delivery for debug traps
Hexagon: set ARCH_DMA_MINALIGN
Hexagon: fix alignment of init_task in RW_DATA_SECTION
hexagon: Fix build failures in linux-next
Diffstat (limited to 'arch/hexagon/include/asm/cacheflush.h')
-rw-r--r-- | arch/hexagon/include/asm/cacheflush.h | 36 |
1 files changed, 19 insertions, 17 deletions
diff --git a/arch/hexagon/include/asm/cacheflush.h b/arch/hexagon/include/asm/cacheflush.h index 49e0896ec240..b86f9f300e94 100644 --- a/arch/hexagon/include/asm/cacheflush.h +++ b/arch/hexagon/include/asm/cacheflush.h @@ -21,10 +21,7 @@ #ifndef _ASM_CACHEFLUSH_H #define _ASM_CACHEFLUSH_H -#include <linux/cache.h> -#include <linux/mm.h> -#include <asm/string.h> -#include <asm-generic/cacheflush.h> +#include <linux/mm_types.h> /* Cache flushing: * @@ -41,6 +38,20 @@ #define LINESIZE 32 #define LINEBITS 5 +#define flush_cache_all() do { } while (0) +#define flush_cache_mm(mm) do { } while (0) +#define flush_cache_dup_mm(mm) do { } while (0) +#define flush_cache_range(vma, start, end) do { } while (0) +#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) +#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 +#define flush_dcache_page(page) do { } while (0) +#define flush_dcache_mmap_lock(mapping) do { } while (0) +#define flush_dcache_mmap_unlock(mapping) do { } while (0) +#define flush_icache_page(vma, pg) do { } while (0) +#define flush_icache_user_range(vma, pg, adr, len) do { } while (0) +#define flush_cache_vmap(start, end) do { } while (0) +#define flush_cache_vunmap(start, end) do { } while (0) + /* * Flush Dcache range through current map. */ @@ -49,7 +60,6 @@ extern void flush_dcache_range(unsigned long start, unsigned long end); /* * Flush Icache range through current map. */ -#undef flush_icache_range extern void flush_icache_range(unsigned long start, unsigned long end); /* @@ -79,19 +89,11 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, /* generic_ptrace_pokedata doesn't wind up here, does it? */ } -#undef copy_to_user_page -static inline void copy_to_user_page(struct vm_area_struct *vma, - struct page *page, - unsigned long vaddr, - void *dst, void *src, int len) -{ - memcpy(dst, src, len); - if (vma->vm_flags & VM_EXEC) { - flush_icache_range((unsigned long) dst, - (unsigned long) dst + len); - } -} +void copy_to_user_page(struct vm_area_struct *vma, struct page *page, + unsigned long vaddr, void *dst, void *src, int len); +#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ + memcpy(dst, src, len) extern void hexagon_inv_dcache_range(unsigned long start, unsigned long end); extern void hexagon_clean_dcache_range(unsigned long start, unsigned long end); |