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| author | Sonic Zhang <sonic.zhang@analog.com> | 2008-10-09 14:11:57 +0800 |
|---|---|---|
| committer | Bryan Wu <cooloney@kernel.org> | 2008-10-09 14:11:57 +0800 |
| commit | f099f39acf7575eff3dee3c562cec4e592876c33 (patch) | |
| tree | 57beb28f62712f061789626ad15eabbe31cc5286 /arch/blackfin/kernel/cplb-mpu | |
| parent | 8606801b0361e0f8520892c9bf524df89c35e690 (diff) | |
| download | talos-obmc-linux-f099f39acf7575eff3dee3c562cec4e592876c33.tar.gz talos-obmc-linux-f099f39acf7575eff3dee3c562cec4e592876c33.zip | |
Blackfin arch: Make L2 SRAM cacheable
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/kernel/cplb-mpu')
| -rw-r--r-- | arch/blackfin/kernel/cplb-mpu/cplbinit.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c index d4257d0ad6a8..55af729f8495 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c @@ -83,8 +83,18 @@ void __init generate_cplb_tables(void) dcplb_tbl[i_d].addr = L1_DATA_A_START; dcplb_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; #endif +#if L1_CODE_LENGTH > 0 icplb_tbl[i_i].addr = L1_CODE_START; icplb_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; +#endif + + /* Cover L2 memory */ +#if L2_LENGTH > 0 + dcplb_tbl[i_d].addr = L2_START; + dcplb_tbl[i_d++].data = L2_DMEMORY | PAGE_SIZE_1MB; + icplb_tbl[i_i].addr = L2_START; + icplb_tbl[i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB; +#endif first_mask_dcplb = i_d; first_switched_dcplb = i_d + (1 << page_mask_order); |
