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| author | Sudeep Holla <sudeep.holla@arm.com> | 2015-06-03 14:31:49 +0100 |
|---|---|---|
| committer | Sudeep Holla <sudeep.holla@arm.com> | 2015-10-09 10:23:49 +0100 |
| commit | 050c69e8769b00645d6723390de6092c9dfcf746 (patch) | |
| tree | 214813281468c3ab41a09f72f3cef8290a0f1f1f /arch/arm64 | |
| parent | ff9a6262b9b87204146427a3abefc73ab990c21f (diff) | |
| download | talos-obmc-linux-050c69e8769b00645d6723390de6092c9dfcf746.tar.gz talos-obmc-linux-050c69e8769b00645d6723390de6092c9dfcf746.zip | |
arm64: dts: add CPU topology on Juno
This patch adds CPU topology on Juno. It will be useful for ther other
IP blocks depending on this topology.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Jon Medhurst (Tixy) <tixy@linaro.org>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/boot/dts/arm/juno-r1.dts | 26 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/arm/juno.dts | 26 |
2 files changed, 52 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts index c62751153a4f..69130840c6cd 100644 --- a/arch/arm64/boot/dts/arm/juno-r1.dts +++ b/arch/arm64/boot/dts/arm/juno-r1.dts @@ -34,6 +34,32 @@ #address-cells = <2>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&A57_0>; + }; + core1 { + cpu = <&A57_1>; + }; + }; + + cluster1 { + core0 { + cpu = <&A53_0>; + }; + core1 { + cpu = <&A53_1>; + }; + core2 { + cpu = <&A53_2>; + }; + core3 { + cpu = <&A53_3>; + }; + }; + }; + A57_0: cpu@0 { compatible = "arm,cortex-a57","arm,armv8"; reg = <0x0 0x0>; diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts index d7cbdd482a61..ce1128a54c8d 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -34,6 +34,32 @@ #address-cells = <2>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&A57_0>; + }; + core1 { + cpu = <&A57_1>; + }; + }; + + cluster1 { + core0 { + cpu = <&A53_0>; + }; + core1 { + cpu = <&A53_1>; + }; + core2 { + cpu = <&A53_2>; + }; + core3 { + cpu = <&A53_3>; + }; + }; + }; + A57_0: cpu@0 { compatible = "arm,cortex-a57","arm,armv8"; reg = <0x0 0x0>; |
