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| author | Marc Zyngier <marc.zyngier@arm.com> | 2017-02-01 11:48:58 +0000 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2017-04-07 11:22:08 +0100 |
| commit | 6126ce0588eb5a0752d5c8b5796a7fca324fd887 (patch) | |
| tree | 7fc0666a03713243eac961d8899109686b12a628 /arch/arm64/include/asm/esr.h | |
| parent | 8f4137588261d7504f4aa022dc9d1a1fd1940e8e (diff) | |
| download | talos-obmc-linux-6126ce0588eb5a0752d5c8b5796a7fca324fd887.tar.gz talos-obmc-linux-6126ce0588eb5a0752d5c8b5796a7fca324fd887.zip | |
arm64: Add CNTVCT_EL0 trap handler
Since people seem to make a point in breaking the userspace visible
counter, we have no choice but to trap the access. Add the required
handler.
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/esr.h')
| -rw-r--r-- | arch/arm64/include/asm/esr.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index d14c478976d0..ad42e79a5d4d 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -175,6 +175,8 @@ #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \ ESR_ELx_SYS64_ISS_DIR_READ) +#define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ + ESR_ELx_SYS64_ISS_DIR_READ) #ifndef __ASSEMBLY__ #include <asm/types.h> |
