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author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-10-11 10:09:45 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-10-11 10:09:45 -0700 |
commit | 7cc4e87f912bbefa440a51856b8d076e5d1f554a (patch) | |
tree | 1b8df8683f3de37d2e8211ffa8d151f60d59af62 /arch/arm/mm/proc-v7.S | |
parent | 5ba2f67afb02c5302b2898949ed6fc3b3d37dcf1 (diff) | |
parent | 69fc7eed5f56bce15b239e5110de2575a6970df4 (diff) | |
download | talos-obmc-linux-7cc4e87f912bbefa440a51856b8d076e5d1f554a.tar.gz talos-obmc-linux-7cc4e87f912bbefa440a51856b8d076e5d1f554a.zip |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (236 commits)
[ARM] 5300/1: fixup spitz reset during boot
[ARM] 5295/1: make ZONE_DMA optional
[ARM] 5239/1: Palm Zire 72 power management support
[ARM] 5298/1: Drop desc_handle_irq()
[ARM] 5297/1: [KS8695] Fix two compile-time warnings
[ARM] 5296/1: [KS8695] Replace macro's with trailing underscores.
[ARM] pxa: allow multi-machine PCMCIA builds
[ARM] pxa: add preliminary CPUFREQ support for PXA3xx
[ARM] pxa: add missing ACCR bit definitions to pxa3xx-regs.h
[ARM] pxa: rename cpu-pxa.c to cpufreq-pxa2xx.c
[ARM] pxa/zylonite: add support for USB OHCI
[ARM] ohci-pxa27x: use ioremap() and offset for register access
[ARM] ohci-pxa27x: introduce pxa27x_clear_otgph()
[ARM] ohci-pxa27x: use platform_get_{irq,resource} for the resource
[ARM] ohci-pxa27x: move OHCI controller specific registers into the driver
[ARM] ohci-pxa27x: introduce flags to avoid direct access to OHCI registers
[ARM] pxa: move I2S register and bit definitions into pxa2xx-i2s.c
[ARM] pxa: simplify DMA register definitions
[ARM] pxa: make additional DCSR bits valid for PXA3xx
[ARM] pxa: move i2c register and bit definitions into i2c-pxa.c
...
Fixed up conflicts in
arch/arm/mach-versatile/core.c
sound/soc/pxa/pxa2xx-ac97.c
sound/soc/pxa/pxa2xx-i2s.c
manually.
Diffstat (limited to 'arch/arm/mm/proc-v7.S')
-rw-r--r-- | arch/arm/mm/proc-v7.S | 39 |
1 files changed, 21 insertions, 18 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index b49f9a4c82c8..34e424041927 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -12,7 +12,7 @@ #include <linux/linkage.h> #include <asm/assembler.h> #include <asm/asm-offsets.h> -#include <asm/elf.h> +#include <asm/hwcap.h> #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> @@ -25,9 +25,11 @@ ENTRY(cpu_v7_proc_init) mov pc, lr +ENDPROC(cpu_v7_proc_init) ENTRY(cpu_v7_proc_fin) mov pc, lr +ENDPROC(cpu_v7_proc_fin) /* * cpu_v7_reset(loc) @@ -43,6 +45,7 @@ ENTRY(cpu_v7_proc_fin) .align 5 ENTRY(cpu_v7_reset) mov pc, r0 +ENDPROC(cpu_v7_reset) /* * cpu_v7_do_idle() @@ -52,8 +55,9 @@ ENTRY(cpu_v7_reset) * IRQs are already disabled. */ ENTRY(cpu_v7_do_idle) - .long 0xe320f003 @ ARM V7 WFI instruction + wfi mov pc, lr +ENDPROC(cpu_v7_do_idle) ENTRY(cpu_v7_dcache_clean_area) #ifndef TLB_CAN_READ_FROM_L1_CACHE @@ -65,6 +69,7 @@ ENTRY(cpu_v7_dcache_clean_area) dsb #endif mov pc, lr +ENDPROC(cpu_v7_dcache_clean_area) /* * cpu_v7_switch_mm(pgd_phys, tsk) @@ -89,6 +94,7 @@ ENTRY(cpu_v7_switch_mm) isb #endif mov pc, lr +ENDPROC(cpu_v7_switch_mm) /* * cpu_v7_set_pte_ext(ptep, pte) @@ -99,26 +105,19 @@ ENTRY(cpu_v7_switch_mm) * (hardware version is stored at -1024 bytes) * - pte - PTE value to store * - ext - value for extended PTE bits - * - * Permissions: - * YUWD APX AP1 AP0 SVC User - * 0xxx 0 0 0 no acc no acc - * 100x 1 0 1 r/o no acc - * 10x0 1 0 1 r/o no acc - * 1011 0 0 1 r/w no acc - * 110x 0 1 0 r/w r/o - * 11x0 0 1 0 r/w r/o - * 1111 0 1 1 r/w r/w */ ENTRY(cpu_v7_set_pte_ext) #ifdef CONFIG_MMU str r1, [r0], #-2048 @ linux version bic r3, r1, #0x000003f0 - bic r3, r3, #0x00000003 + bic r3, r3, #PTE_TYPE_MASK orr r3, r3, r2 orr r3, r3, #PTE_EXT_AP0 | 2 + tst r2, #1 << 4 + orrne r3, r3, #PTE_EXT_TEX(1) + tst r1, #L_PTE_WRITE tstne r1, #L_PTE_DIRTY orreq r3, r3, #PTE_EXT_APX @@ -128,19 +127,18 @@ ENTRY(cpu_v7_set_pte_ext) tstne r3, #PTE_EXT_APX bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 - tst r1, #L_PTE_YOUNG - biceq r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK - tst r1, #L_PTE_EXEC orreq r3, r3, #PTE_EXT_XN - tst r1, #L_PTE_PRESENT + tst r1, #L_PTE_YOUNG + tstne r1, #L_PTE_PRESENT moveq r3, #0 str r3, [r0] mcr p15, 0, r0, c7, c10, 1 @ flush_pte #endif mov pc, lr +ENDPROC(cpu_v7_set_pte_ext) cpu_v7_name: .ascii "ARMv7 Processor" @@ -182,12 +180,17 @@ __v7_setup: mov r10, #0x1f @ domains 0, 1 = manager mcr p15, 0, r10, c3, c0, 0 @ load domain access register #endif + ldr r5, =0x40e040e0 + ldr r6, =0xff0aa1a8 + mcr p15, 0, r5, c10, c2, 0 @ write PRRR + mcr p15, 0, r6, c10, c2, 1 @ write NMRR adr r5, v7_crval ldmia r5, {r5, r6} mrc p15, 0, r0, c1, c0, 0 @ read control register bic r0, r0, r5 @ clear bits them orr r0, r0, r6 @ set them mov pc, lr @ return to head.S:__ret +ENDPROC(__v7_setup) /* * V X F I D LR @@ -197,7 +200,7 @@ __v7_setup: */ .type v7_crval, #object v7_crval: - crval clear=0x0120c302, mmuset=0x00c0387d, ucset=0x00c0187c + crval clear=0x0120c302, mmuset=0x10c0387d, ucset=0x00c0187c __v7_setup_stack: .space 4 * 11 @ 11 registers |