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| author | Leif Lindholm <leif.lindholm@arm.com> | 2010-09-16 18:00:47 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-11-04 15:45:24 +0000 |
| commit | 64d2dc384e41e2b7acead6804593ddaaf8aad8e1 (patch) | |
| tree | 07f6e34981bd4a6642cdffb546b32a2a973aec5d /arch/arm/mm/proc-v7.S | |
| parent | 247055aa21ffef1c49dd64710d5e94c2aee19b58 (diff) | |
| download | talos-obmc-linux-64d2dc384e41e2b7acead6804593ddaaf8aad8e1.tar.gz talos-obmc-linux-64d2dc384e41e2b7acead6804593ddaaf8aad8e1.zip | |
ARM: 6396/1: Add SWP/SWPB emulation for ARMv7 processors
The SWP instruction was deprecated in the ARMv6 architecture,
superseded by the LDREX/STREX family of instructions for
load-linked/store-conditional operations. The ARMv7 multiprocessing
extensions mandate that SWP/SWPB instructions are treated as undefined
from reset, with the ability to enable them through the System Control
Register SW bit.
This patch adds the alternative solution to emulate the SWP and SWPB
instructions using LDREX/STREX sequences, and log statistics to
/proc/cpu/swp_emulation. To correctly deal with copy-on-write, it also
modifies cpu_v7_set_pte_ext to change the mappings to priviliged RO when
user RO.
Signed-off-by: Leif Lindholm <leif.lindholm@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Kirill A. Shutemov <kirill@shutemov.name>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-v7.S')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index cfc11afab1fb..2b5b20baf80d 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -314,6 +314,10 @@ __v7_setup: #ifdef CONFIG_CPU_ENDIAN_BE8 orr r6, r6, #1 << 25 @ big-endian page tables #endif +#ifdef CONFIG_SWP_EMULATE + orr r5, r5, #(1 << 10) @ set SW bit in "clear" + bic r6, r6, #(1 << 10) @ clear it in "mmuset" +#endif mrc p15, 0, r0, c1, c0, 0 @ read control register bic r0, r0, r5 @ clear bits them orr r0, r0, r6 @ set them |
