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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-01-09 08:58:57 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-01-09 08:58:57 -0800 |
| commit | 5c49985c21bba4d2f899e3a97121868a5c58a876 (patch) | |
| tree | f877cde6c0effa6c8cd6e1d0d7e116358eb41ee8 /arch/arm/mm/proc-v7.S | |
| parent | 57a0c1e2d6cb70ad0f8549ae730fc58fd0553429 (diff) | |
| parent | 8a3a180d21793f2e4386b3cb61c48322564fc80a (diff) | |
| download | talos-obmc-linux-5c49985c21bba4d2f899e3a97121868a5c58a876.tar.gz talos-obmc-linux-5c49985c21bba4d2f899e3a97121868a5c58a876.zip | |
Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm
Pull ARM fixes from Russell King.
* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
ARM: 7616/1: cache-l2x0: aurora: Use writel_relaxed instead of writel
ARM: 7615/1: cache-l2x0: aurora: Invalidate during clean operation with WT enable
ARM: 7614/1: mm: fix wrong branch from Cortex-A9 to PJ4b
ARM: 7612/1: imx: Do not select some errata that depends on !ARCH_MULTIPLATFORM
ARM: 7611/1: VIC: fix bug in VIC irqdomain code
ARM: 7610/1: versatile: bump IRQ numbers
ARM: 7609/1: disable errata work-arounds which access secure registers
ARM: 7608/1: l2x0: Only set .set_debug on PL310 r3p0 and earlier
Diffstat (limited to 'arch/arm/mm/proc-v7.S')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 350f6a74992b..3a3c015f8d5c 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -169,6 +169,7 @@ __v7_ca15mp_setup: orreq r0, r0, r10 @ Enable CPU-specific SMP bits mcreq p15, 0, r0, c1, c0, 1 #endif + b __v7_setup __v7_pj4b_setup: #ifdef CONFIG_CPU_PJ4B @@ -245,7 +246,8 @@ __v7_setup: ldr r10, =0x00000c08 @ Cortex-A8 primary part number teq r0, r10 bne 2f -#ifdef CONFIG_ARM_ERRATA_430973 +#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM) + teq r5, #0x00100000 @ only present in r1p* mrceq p15, 0, r10, c1, c0, 1 @ read aux control register orreq r10, r10, #(1 << 6) @ set IBE to 1 |
