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| author | Thierry Reding <thierry.reding@avionic-design.de> | 2011-12-16 21:01:57 +0100 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2012-07-02 15:01:34 -0600 |
| commit | 094479915618c526a1409dd6704bcb4ff2c5c1c2 (patch) | |
| tree | 7e1f8e656bb77519cd8f6b2004a6e01b8be3703b /arch/arm/mach-tegra/tegra30_clocks.c | |
| parent | bb1dccfc63f7a007c6347c75ba597d866749d9d2 (diff) | |
| download | talos-obmc-linux-094479915618c526a1409dd6704bcb4ff2c5c1c2.tar.gz talos-obmc-linux-094479915618c526a1409dd6704bcb4ff2c5c1c2.zip | |
ARM: tegra: Provide clock for only one PWM controller
A subsequent patch will add a generic PWM API driver for the Tegra PWFM
controller, supporting all four PWM devices with a single PWM chip. The
device will be named tegra-pwm and only one clock needs to be provided.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra30_clocks.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra30_clocks.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c index 2ba948ea21ff..6674f100e16f 100644 --- a/arch/arm/mach-tegra/tegra30_clocks.c +++ b/arch/arm/mach-tegra/tegra30_clocks.c @@ -2886,7 +2886,7 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), @@ -2990,10 +2990,6 @@ struct clk_duplicate tegra_clk_duplicates[] = { CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"), CLK_DUPLICATE("dsib", "tegradc.0", "dsib"), CLK_DUPLICATE("dsia", "tegradc.1", "dsia"), - CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL), - CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL), - CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL), - CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL), CLK_DUPLICATE("bsev", "tegra-avp", "bsev"), CLK_DUPLICATE("bsev", "nvavp", "bsev"), CLK_DUPLICATE("vde", "tegra-aes", "vde"), |
