diff options
| author | Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> | 2010-10-18 22:41:29 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-12-21 14:53:45 +0000 |
| commit | fa87672ab30ce6564393778b8cbc67fc32712a30 (patch) | |
| tree | 50551c8763a12f37ef483055aa0e53b4f894776a /arch/arm/mach-sa1100/include | |
| parent | 17b38ebb6a32250a220d6af77293f7e3f9c62a6e (diff) | |
| download | talos-obmc-linux-fa87672ab30ce6564393778b8cbc67fc32712a30.tar.gz talos-obmc-linux-fa87672ab30ce6564393778b8cbc67fc32712a30.zip | |
ARM: 6458/1: pcmcia: Adds nanoEngine PCMCIA support.
This patch adds nanoEngine PCMCIA support, with support for two sockets.
In order to have a fully functional pcmcia subsystem in a BSE
nanoEngine board you should carefully read this:
http://cambuca.ldhs.cetuc.puc-rio.br/nanoengine/
Acked-by: Dominik Brodowski <linux@dominikbrodowski.net>
Signed-off-by: Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-sa1100/include')
| -rw-r--r-- | arch/arm/mach-sa1100/include/mach/nanoengine.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/mach-sa1100/include/mach/nanoengine.h b/arch/arm/mach-sa1100/include/mach/nanoengine.h new file mode 100644 index 000000000000..053776645526 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/nanoengine.h @@ -0,0 +1,30 @@ +/* + * arch/arm/mach-sa1100/include/mach/nanoengine.h + * + * This file contains the hardware specific definitions for nanoEngine. + * Only include this file from SA1100-specific files. + * + * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef __ASM_ARCH_NANOENGINE_H +#define __ASM_ARCH_NANOENGINE_H + +#define GPIO_PC_READY0 GPIO_GPIO(11) /* ready for socket 0 (active high)*/ +#define GPIO_PC_READY1 GPIO_GPIO(12) /* ready for socket 1 (active high) */ +#define GPIO_PC_CD0 GPIO_GPIO(13) /* detect for socket 0 (active low) */ +#define GPIO_PC_CD1 GPIO_GPIO(14) /* detect for socket 1 (active low) */ +#define GPIO_PC_RESET0 GPIO_GPIO(15) /* reset socket 0 */ +#define GPIO_PC_RESET1 GPIO_GPIO(16) /* reset socket 1 */ + +#define NANOENGINE_IRQ_GPIO_PC_READY0 IRQ_GPIO11 +#define NANOENGINE_IRQ_GPIO_PC_READY1 IRQ_GPIO12 +#define NANOENGINE_IRQ_GPIO_PC_CD0 IRQ_GPIO13 +#define NANOENGINE_IRQ_GPIO_PC_CD1 IRQ_GPIO14 + +#endif + |
