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| author | R Sricharan <r.sricharan@ti.com> | 2013-10-10 13:13:48 +0530 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2013-10-10 10:14:22 -0700 |
| commit | 5523e4092ee4f2ef58d00c78365c8bddf730c900 (patch) | |
| tree | ddca2e68a02c282bdf8034e08fcd7286f054b39b /arch/arm/mach-omap2/timer.c | |
| parent | aa2f4b16f8305f0bddb5731a222b0ce39e6844aa (diff) | |
| download | talos-obmc-linux-5523e4092ee4f2ef58d00c78365c8bddf730c900.tar.gz talos-obmc-linux-5523e4092ee4f2ef58d00c78365c8bddf730c900.zip | |
ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register
The realtime counter called master counter, produces the count
used by the private timer peripherals in the MPU_CLUSTER. The
CNTFRQ per cpu register is used to denote the frequency of the counter.
Currently the frequency value is passed from the
DT file, but this is not scalable when we have other non-DT guest
OS. This register must be set to the right value by the
secure rom code. Setting this register helps in propagating the right
frequency value across OSes.
More discussions and the reason for adding this in a non-DT
way can be seen from below.
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg93832.html
So configuring this secure register for all the cpus here.
Cc: Nishanth Menon <nm@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/timer.c')
| -rw-r--r-- | arch/arm/mach-omap2/timer.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index d0f80c020423..87259dc82aa2 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -55,6 +55,7 @@ #include "soc.h" #include "common.h" #include "powerdomain.h" +#include "omap-secure.h" #define REALTIME_COUNTER_BASE 0x48243200 #define INCREMENTER_NUMERATOR_OFFSET 0x10 @@ -65,6 +66,12 @@ static struct omap_dm_timer clkev; static struct clock_event_device clockevent_gpt; +static unsigned long arch_timer_freq; + +void set_cntfreq(void) +{ + omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq); +} static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) { @@ -546,6 +553,9 @@ static void __init realtime_counter_init(void) reg |= den; __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); + arch_timer_freq = (rate / den) * num; + set_cntfreq(); + iounmap(base); } #else |
