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| author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2011-06-06 14:33:29 +0530 |
|---|---|---|
| committer | Kevin Hilman <khilman@ti.com> | 2011-12-08 11:29:01 -0800 |
| commit | 3ba2a7393e6be48ad7f545a743cd6f46325ba8fd (patch) | |
| tree | 6bd945957e1b7bd526419ca67e9dbd6072ccdaa2 /arch/arm/mach-omap2/common.h | |
| parent | 5e94c6e33e7c4726ef09f46c267e9ca232c5148a (diff) | |
| download | talos-obmc-linux-3ba2a7393e6be48ad7f545a743cd6f46325ba8fd.tar.gz talos-obmc-linux-3ba2a7393e6be48ad7f545a743cd6f46325ba8fd.zip | |
ARM: OMAP4: PM: Add MPUSS power domain OSWR support
This patch adds the MPUSS OSWR (Open Switch Retention) support. The MPUSS
OSWR configuration is as below.
- CPUx L1 and logic lost, MPUSS logic lost, L2 memory is retained
OMAP4460 onwards, MPUSS power domain doesn't support OFF state any more
anymore just like CORE power domain. The deepest state supported is OSWR.
On OMAP4430 secure devices too, MPUSS off mode can't be used because of
a bug which alters Ducati and Tesla states. Hence MPUSS off mode as an
independent state isn't supported on OMAP44XX devices.
Ofcourse when MPUSS power domain transitions to OSWR along
with device off mode, it eventually hits off state since memory
contents are lost.
Hence the MPUSS off mode independent state is not attempted without
device off mode. All the necessary infrastructure code for MPUSS
off mode is in place as part of this series.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/common.h')
| -rw-r--r-- | arch/arm/mach-omap2/common.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 3312174d64ba..0911e843f079 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -190,6 +190,7 @@ extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state); extern int omap4_finish_suspend(unsigned long cpu_state); extern void omap4_cpu_resume(void); extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state); +extern u32 omap4_mpuss_read_prev_context_state(void); #else static inline int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) @@ -216,6 +217,11 @@ static inline int omap4_finish_suspend(unsigned long cpu_state) static inline void omap4_cpu_resume(void) {} + +static inline u32 omap4_mpuss_read_prev_context_state(void) +{ + return 0; +} #endif #endif /* __ASSEMBLER__ */ #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */ |
