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| author | Javier Martinez Canillas <javier@dowhile0.org> | 2012-07-30 17:59:48 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-07-31 12:06:27 +0100 |
| commit | 89269ef1f0abc72c551198123e19cd4edfd43cf4 (patch) | |
| tree | 7e0d58aaf8cc922d0582f286742f9dfe935354b5 /arch/arm/configs | |
| parent | 04e8c7bc2c1eda2d06ff6eb57a7df97e64d895e6 (diff) | |
| download | talos-obmc-linux-89269ef1f0abc72c551198123e19cd4edfd43cf4.tar.gz talos-obmc-linux-89269ef1f0abc72c551198123e19cd4edfd43cf4.zip | |
ARM: 7481/1: OMAP2+: omap2plus_defconfig: enable OMAP DMA engine
commit 13f30fc893e4610f67dd7a8b0b67aec02eac1775
Author: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Sat Apr 21 22:41:10 2012 +0100
mmc: omap: remove private DMA API implementation
removed the private DMA API implementation from the OMAP mmc host to exclusively use the DMA engine API.
Unfortunately OMAP MMC and High Speed MMC host drivers don't support poll mode and only works with DMA.
Since omap2plus_defconfig doesn't enable this feature by default, the
following error is happens on an IGEPv2 Rev.C (and probably on most OMAP boards with MMC support):
[ 2.199981] omap_hsmmc omap_hsmmc.1: unable to obtain RX DMA engine channel 48
[ 2.215087] omap_hsmmc omap_hsmmc.0: unable to obtain RX DMA engine channel 62
Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/configs')
| -rw-r--r-- | arch/arm/configs/omap2plus_defconfig | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 9854ff4279e0..3b391b23bdda 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -194,6 +194,8 @@ CONFIG_MMC_OMAP_HS=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_TWL92330=y CONFIG_RTC_DRV_TWL4030=y +CONFIG_DMADEVICES=y +CONFIG_DMA_OMAP=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set |
