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authorSrinivas Kandagatla <srinivas.kandagatla@linaro.org>2016-02-23 14:14:50 +0000
committerAndy Gross <andy.gross@linaro.org>2016-02-26 13:15:49 -0600
commit2a5cbc15326a2fa6b2a826b2d27f9061dde81a0a (patch)
treed719894043d635a3567625e22fb998b709c27bf3 /arch/arm/boot/dts/qcom-apq8064.dtsi
parent7788d439ae08852cf5b54260b2132401761b745a (diff)
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ARM: dts: apq8064: add gsbi4 with i2c node.
This patch adds gsbi4 and i2c node. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/qcom-apq8064.dtsi')
-rw-r--r--arch/arm/boot/dts/qcom-apq8064.dtsi23
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 20da87306bb3..766fead5d4e3 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -289,6 +289,29 @@
};
};
+ gsbi4: gsbi@16300000 {
+ status = "disabled";
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <4>;
+ reg = <0x16300000 0x03>;
+ clocks = <&gcc GSBI4_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gsbi4_i2c: i2c@16380000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ pinctrl-0 = <&i2c4_pins &i2c4_pins_sleep>;
+ pinctrl-names = "default", "sleep";
+ reg = <0x16380000 0x1000>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
+ clocks = <&gcc GSBI4_QUP_CLK>,
+ <&gcc GSBI4_H_CLK>;
+ clock-names = "core", "iface";
+ };
+ };
+
gsbi5: gsbi@1a200000 {
status = "disabled";
compatible = "qcom,gsbi-v1.0.0";
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