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| author | Marcin Wojtas <mw@semihalf.com> | 2016-03-14 09:38:58 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2016-03-14 12:19:45 -0400 |
| commit | c49e99c2b25a412623412a461bb751239208b9b3 (patch) | |
| tree | 4b87acc16f414c909e891be8901d455d50e260d2 /arch/arm/boot/dts/armada-388-gp.dts | |
| parent | 4a547a5a46d05442a767b8ea8b8feb2a5bd76585 (diff) | |
| download | talos-obmc-linux-c49e99c2b25a412623412a461bb751239208b9b3.tar.gz talos-obmc-linux-c49e99c2b25a412623412a461bb751239208b9b3.zip | |
ARM: dts: armada-38x: enable buffer manager support on Armada 38x boards
Since mvneta driver supports using hardware buffer management (BM), in
order to use it, board files have to be adjusted accordingly. This commit
enables BM on:
* A385-DB-AP - each port has its own pool for long and common pool for
short packets,
* A388-ClearFog - same as above,
* A388-DB - to each port unique 'short' and 'long' pools are mapped,
* A388-GP - same as above.
Moreover appropriate entry is added to 'soc' node ranges, as well as "okay"
status for 'bm' and 'bm-bppi' (internal SRAM) nodes.
[gregory.clement@free-electrons.com: add suppport for the ClearFog board]
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/arm/boot/dts/armada-388-gp.dts')
| -rw-r--r-- | arch/arm/boot/dts/armada-388-gp.dts | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts index cd316021d6ce..466b01eb1038 100644 --- a/arch/arm/boot/dts/armada-388-gp.dts +++ b/arch/arm/boot/dts/armada-388-gp.dts @@ -60,7 +60,8 @@ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 - MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>; + MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000 + MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>; internal-regs { spi@10600 { @@ -133,6 +134,9 @@ status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; + buffer-manager = <&bm>; + bm,pool-long = <2>; + bm,pool-short = <3>; }; /* CON4 */ @@ -152,6 +156,9 @@ status = "okay"; phy = <&phy0>; phy-mode = "rgmii-id"; + buffer-manager = <&bm>; + bm,pool-long = <0>; + bm,pool-short = <1>; }; @@ -186,6 +193,10 @@ }; }; + bm@c8000 { + status = "okay"; + }; + sata@e0000 { pinctrl-names = "default"; pinctrl-0 = <&sata2_pins>, <&sata3_pins>; @@ -240,6 +251,10 @@ }; }; + bm-bppi { + status = "okay"; + }; + pcie-controller { status = "okay"; /* |
