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| author | Tero Kristo <t-kristo@ti.com> | 2014-02-21 17:36:21 +0200 |
|---|---|---|
| committer | Tero Kristo <t-kristo@ti.com> | 2014-05-28 12:28:20 +0300 |
| commit | aa76fcf473f6bfa839f37f77b6fdb71f0fb88d8f (patch) | |
| tree | d8696ea988e4a1e54e6017b31fd8fd268a97a76a /Documentation/devicetree | |
| parent | a6fe3771d389cc660933509b7dfb945c596636f5 (diff) | |
| download | talos-obmc-linux-aa76fcf473f6bfa839f37f77b6fdb71f0fb88d8f.tar.gz talos-obmc-linux-aa76fcf473f6bfa839f37f77b6fdb71f0fb88d8f.zip | |
CLK: TI: DPLL: add support for omap2 core dpll
OMAP2 has slightly different DPLL compared to later OMAP generations.
This patch adds support for the ti,omap2-dpll-core-clock and also adds
the bindings documentation.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/ti/dpll.txt | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt index 30bfdb7c9f18..50a1a427608f 100644 --- a/Documentation/devicetree/bindings/clock/ti/dpll.txt +++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt @@ -30,6 +30,7 @@ Required properties: "ti,am3-dpll-clock", "ti,am3-dpll-core-clock", "ti,am3-dpll-x2-clock", + "ti,omap2-dpll-core-clock", - #clock-cells : from common clock binding; shall be set to 0. - clocks : link phandles of parent clocks, first entry lists reference clock @@ -41,6 +42,7 @@ Required properties: "mult-div1" - contains the multiplier / divider register base address "autoidle" - contains the autoidle register base address (optional) ti,am3-* dpll types do not have autoidle register + ti,omap2-* dpll type does not support idlest / autoidle registers Optional properties: - DPLL mode setting - defining any one or more of the following overrides @@ -73,3 +75,10 @@ Examples: clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x90>, <0x5c>, <0x68>; }; + + dpll_ck: dpll_ck { + #clock-cells = <0>; + compatible = "ti,omap2-dpll-core-clock"; + clocks = <&sys_ck>, <&sys_ck>; + reg = <0x0500>, <0x0540>; + }; |
