1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
|
<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_read_seeprom_errors.xml $ -->
<!-- -->
<!-- OpenPOWER HostBoot Project -->
<!-- -->
<!-- COPYRIGHT International Business Machines Corp. 2012,2014 -->
<!-- -->
<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
<!-- you may not use this file except in compliance with the License. -->
<!-- You may obtain a copy of the License at -->
<!-- -->
<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
<!-- -->
<!-- Unless required by applicable law or agreed to in writing, software -->
<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
<!-- implied. See the License for the specific language governing -->
<!-- permissions and limitations under the License. -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
<!-- $Id: proc_read_seeprom_errors.xml,v 1.3 2013/07/26 22:46:42 rjknight Exp $ -->
<!-- Error definitions for proc_read_seeprom procedure -->
<hwpErrors>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_PIB_BUS_ADDR_NVLD_ERR_BIT_SET</rc>
<description>Invalid address from PIB</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_PIB_BUS_WRITE_NVLD_ERR_BIT_SET</rc>
<description>Invalid write from PIB</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_PIB_BUS_READ_NVLD_ERR_BIT_SET</rc>
<description>Invalid read from PIB</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_PIB_BUS_ADDR_PAR_ERR_BIT_SET</rc>
<description>Address parity error from PIB</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_PIB_BUS_PAR_ERR_BIT_SET</rc>
<description>Parity error form PIB</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_LOCAL_BUS_PAR_ERR_BIT_SET</rc>
<description>A parity error on LB between I2C and PIB occurred</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_PIB_INVALID_COMMAND_BIT_SET</rc>
<description>Bit 45 of status register set</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_PIB_PARITY_ERR_BIT_SET</rc>
<description>Bit 46 of status register set</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_I2C_BACK_END_OVERRUN_ERR_BIT_SET</rc>
<description>Bit 47 of status register set</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_I2C_BACK_END_ACCESS_ERR_BIT_SET</rc>
<description>Bit 48 of status register set</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_I2C_ARBITRATION_LOST_ERR_BIT_SET</rc>
<description>Bit 49 of status register set</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_I2C_NACK_RECIEVED_ERR_BIT_SET</rc>
<description>Bit 50 of status register set</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_I2C_COMMAND_COMPLETE_NOT_SET</rc>
<description>Bit 52 of status register not set after bit 44 is cleared</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_I2C_COMMAND_COMPLETE_TIME_OUT</rc>
<description>Bit 52 of status register not set and time out after certain time</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_I2C_STOP_ERR_BIT_SET</rc>
<description>Bit 53 of status register set</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_PARITY_ERROR_BIT_SET</rc>
<description>Bit 56 of status register set</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_CE_COUNTER_OVERFLOW_BIT_SET</rc>
<description>Bit 57 of status register set</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_PIB_MASTER_RESP_INFO_BITS_SET</rc>
<description>Some bits between 38 to 40 of status register set</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_PIB_CONTROL_REG_DATA_LGT_ERR</rc>
<description>Bits 41:43 equal 100, control reg data length err</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_PIB_CONTROL_REG_ADD_LGT_ERR</rc>
<description>Bit 41:43 equal 101, control reg address length err</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_PIB_CONTROL_REG_ADDR_BDY_ERR</rc>
<description>Bit 41:43 equal 110, control reg address boudary err</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_PIB_ECCADDR_REG_ERR</rc>
<description>Bit 41:43 equal 111, ecc address register err</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_PIB_EFF_PIBM_RESET</rc>
<description>Bit 41:43 equal 010,pib master reset</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_PIB_UEC_Q</rc>
<description>Bit 41:43 equal 001, uncorrectable ecc error</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_READ_SEEPROM_PIB_SLAVE_RESET</rc>
<description>Bit 41:43 equal 011, reset from pib slave</description>
</hwpError>
</hwpErrors>
|
