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<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
<!-- This is an automatically generated prolog.                             -->
<!--                                                                        -->
<!-- $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.xml $ -->
<!--                                                                        -->
<!-- OpenPOWER HostBoot Project                                             -->
<!--                                                                        -->
<!-- Contributors Listed Below - COPYRIGHT 2014                             -->
<!-- [+] International Business Machines Corp.                              -->
<!--                                                                        -->
<!--                                                                        -->
<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
<!-- you may not use this file except in compliance with the License.       -->
<!-- You may obtain a copy of the License at                                -->
<!--                                                                        -->
<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
<!--                                                                        -->
<!-- Unless required by applicable law or agreed to in writing, software    -->
<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
<!-- implied. See the License for the specific language governing           -->
<!-- permissions and limitations under the License.                         -->
<!--                                                                        -->
<!-- IBM_PROLOG_END_TAG                                                     -->
<!-- $Id: proc_extract_pore_base_ffdc.xml,v 1.1 2014/07/23 19:43:18 jmcgill Exp $ -->
<!-- Error definitions for proc_extract_pore_base_ffdc procedure -->
<hwpErrors>
  <!-- *********************************************************************** -->
  <hwpError>
    <rc>RC_PROC_EXTRACT_PORE_BASE_FFDC</rc>
    <description>
      Base error code used to invoke PORE engine state FFDC logging function
    </description>
    <collectFfdc>proc_extract_pore_base_ffdc, pore_state, pore_sbe_state</collectFfdc>
  </hwpError>
  <!-- *********************************************************************** -->
  <hwpError>
    <rc>RC_PROC_EXTRACT_PORE_BASE_FFDC_ENGINE_STATE</rc>
    <description>
      PORE engine state collected on all SBE/SLW fails
    </description>
    <!-- target/engine type -->
    <ffdc>CHIP</ffdc>
    <ffdc>ENGINE</ffdc>
    <ffdc>VIRTUAL</ffdc>
    <!-- SBE/SLW vital state -->
    <ffdc>PORE_VITAL_REG</ffdc>
    <!-- PORE register state -->
    <ffdc>PORE_STATUS_REG</ffdc>
    <ffdc>PORE_CONTROL_REG</ffdc>
    <ffdc>PORE_RESET_REG</ffdc>
    <ffdc>PORE_ERR_MASK_REG</ffdc>
    <ffdc>PORE_P0_REG</ffdc>
    <ffdc>PORE_P1_REG</ffdc>
    <ffdc>PORE_A0_REG</ffdc>
    <ffdc>PORE_A1_REG</ffdc>
    <ffdc>PORE_TBL_BASE_REG</ffdc>
    <ffdc>PORE_EXE_TRIGGER_REG</ffdc>
    <ffdc>PORE_CTR_REG</ffdc>
    <ffdc>PORE_D0_REG</ffdc>
    <ffdc>PORE_D1_REG</ffdc>
    <ffdc>PORE_IBUF0_REG</ffdc>
    <ffdc>PORE_IBUF1_REG</ffdc>
    <ffdc>PORE_DEBUG0_REG</ffdc>
    <ffdc>PORE_DEBUG1_REG</ffdc>
    <ffdc>PORE_STACK0_REG</ffdc>
    <ffdc>PORE_STACK1_REG</ffdc>
    <ffdc>PORE_STACK2_REG</ffdc>
    <ffdc>PORE_IDFLAGS_REG</ffdc>
    <ffdc>PORE_SPRG0_REG</ffdc>
    <ffdc>PORE_MRR_REG</ffdc>
    <ffdc>PORE_I2CE0_REG</ffdc>
    <ffdc>PORE_I2CE1_REG</ffdc>
    <ffdc>PORE_I2CE2_REG</ffdc>
    <!-- PORE engine PC -->
    <ffdc>PORE_PC</ffdc>
    <!-- RC associated with SBE/SLW halt point -->
    <ffdc>PORE_RC</ffdc>
  </hwpError>
  <!-- *********************************************************************** -->
  <hwpError>
    <rc>RC_PROC_EXTRACT_PORE_BASE_FFDC_SBE</rc>
    <description>
      SBE specific register FFDC to collect (via chip target) on all fails
    </description>
    <ffdc>PNOR_ECCB_STATUS</ffdc>
    <ffdc>SEEPROM_ECCB_STATUS</ffdc>
    <ffdc>SOFT_ERROR_STATUS</ffdc>
    <ffdc>ATTN_REPORTED</ffdc>
    <collectRegisterFfdc>
      <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
      <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
      <target>CHIP</target>
    </collectRegisterFfdc>
    <collectFfdc>proc_tp_collect_dbg_data, CHIP</collectFfdc>
  </hwpError>    
  <!-- *********************************************************************** -->
  <hwpError>
    <rc>RC_PROC_EXTRACT_PORE_BASE_FFDC_SLW</rc>
    <description>
      SLW specific register FFDC to collect (via chip target) on all fails
    </description>
    <collectRegisterFfdc>
      <id>REG_FFDC_PROC_SLW_PBA_REGISTERS</id>
      <id>REG_FFDC_PROC_SLW_FIR_REGISTERS</id>
      <id>REG_FFDC_PROC_SLW_PMC_REGISTERS</id>
      <target>CHIP</target>
    </collectRegisterFfdc>
    <collectRegisterFfdc>
      <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id>
      <basedOnPresentChildren>
        <target>CHIP</target>
        <childType>TARGET_TYPE_EX_CHIPLET</childType>
        <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier>
      </basedOnPresentChildren>     
    </collectRegisterFfdc>
  </hwpError>
  <!-- *********************************************************************** -->
</hwpErrors>
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