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<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: src/usr/hwpf/hwp/runtime_errors/p8_pmc_errors.xml $ -->
<!-- -->
<!-- IBM CONFIDENTIAL -->
<!-- -->
<!-- COPYRIGHT International Business Machines Corp. 2012,2014 -->
<!-- -->
<!-- p1 -->
<!-- -->
<!-- Object Code Only (OCO) source materials -->
<!-- Licensed Internal Code Source Materials -->
<!-- IBM HostBoot Licensed Internal Code -->
<!-- -->
<!-- The source code for this program is not published or otherwise -->
<!-- divested of its trade secrets, irrespective of what has been -->
<!-- deposited with the U.S. Copyright Office. -->
<!-- -->
<!-- Origin: 30 -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
<!-- $Id: p8_pmc_errors.xml,v 1.10 2014/03/10 15:04:05 stillgs Exp $ -->
<!-- Error definitions for proc_pmc_init and proc_pm_init procedure -->
<hwpErrors>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMC_CODE_BAD_MODE</rc>
<description>Unknown mode passed to proc_pmc_init.</description>
<ffdc>MODE</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMCINIT_TIMEOUT</rc>
<description>time out in polling some register condition.</description>
<callout>
<procedure>CHIP_IN_ERROR</procedure>
<priority>HIGH</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMCRESET_SPIVID_CONFIG_ERROR</rc>
<description>Master target does not have SPIVID ports enabled: check the configuration setup.</description>
<ffdc>MASTER_TARGET</ffdc>
<ffdc>ATTR_SPIVID_PORT_ENABLE</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMCRESET_SCM_INSTALL_ERROR</rc>
<description>Error found in DCM installment attribute settings for the SCM case.</description>
<ffdc>MASTER_TARGET</ffdc>
<ffdc>SLAVE_TARGET</ffdc>
<ffdc>DCM_INSTALLED_1</ffdc>
<ffdc>DCM_INSTALLED_2</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMCRESET_DCM_INSTALL_ERROR</rc>
<description>Error found in DCM installment attribute settings.</description>
<ffdc>MASTER_TARGET</ffdc>
<ffdc>SLAVE_TARGET</ffdc>
<ffdc>DCM_INSTALLED_1</ffdc>
<ffdc>DCM_INSTALLED_2</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMC_MASTER_CONFIG_ERROR</rc>
<description>MasterPMC bit of Master PMC is not set.</description>
<ffdc>MASTERPMCMODE</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMC_SLAVE_CONFIG_ERROR</rc>
<description>MasterPMC bit of Slave PMC is not set.</description>
<ffdc>SLAVEPMCMODE</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMC_INTERCHIP_CONFIG_ERROR</rc>
<description>Master is enabled with interchip interface but slave is not.</description>
<ffdc>MASTERPMCMODE</ffdc>
<ffdc>SLAVEPMCMODE</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMC_FW_MODE_ERROR</rc>
<description>Master is enabled with FW pstate mode but slave is not </description>
<ffdc>MASTERPMCMODE</ffdc>
<ffdc>SLAVEPMCMODE</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMCRESET_IDLE_ERROR</rc>
<description>PMC Idle halt errors exist. OCC recovery cannot proceed.</description>
<ffdc>TARGET</ffdc>
<ffdc>PORR</ffdc>
<ffdc>PMCSTATUS</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMCRESET_IDLE_TIMEOUT_ERROR</rc>
<description>Timed out in polling for Idle to Halt. OCC recovery cannot proceed </description>
<ffdc>TARGET</ffdc>
<ffdc>PORR</ffdc>
<ffdc>PMCSTATUS</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMCRESET_SPIVID_TIMEOUT_ERROR</rc>
<description>Timed out in polling for SPIVID controller to Halt. OCC reset is suspious but carried out</description>
<collectRegisterFfdc>
<id>REG_FFDC_SPIVID_REGISTERS</id>
<target>TARGET</target>
</collectRegisterFfdc>
<!-- No callout as this only logs data for use if the PMC reset (part of the OCC reset) actually fails -->
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMCRESET_INTCHP_TIMEOUT_ERROR</rc>
<description>Timed out in polling for InterChip Interface to Halt. OCC reset is suspious but carried out</description>
<collectRegisterFfdc>
<id>REG_FFDC_PSTATE_REGISTERS</id>
<id>REG_FFDC_SPIVID_REGISTERS</id>
<target>THISTARGET</target>
</collectRegisterFfdc>
<collectRegisterFfdc>
<id>REG_FFDC_PSTATE_REGISTERS</id>
<id>REG_FFDC_SPIVID_REGISTERS</id>
<target>DCMTARGET</target>
</collectRegisterFfdc>
<!-- No callout as this only logs data for use if the PMC reset (part of the OCC reset) actually fails -->
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMCRESET_O2P_TIMEOUT_ERROR</rc>
<description>Timed out in polling for OCI to PIB Bridge to Halt. OCC reset is suspious but carried out</description>
<ffdc>TARGET</ffdc>
<ffdc>O2PSTATUS</ffdc>
<!-- No callout as this only logs data for use if the PMC reset (part of the OCC reset) actually fails -->
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMCINIT_SCM_INSTALL_ERROR</rc>
<description>Error found in DCM installment attribute settings for the SCM case in the PMC INIT phase..</description>
<ffdc>MASTER_TARGET</ffdc>
<ffdc>SLAVE_TARGET</ffdc>
<ffdc>DCM_INSTALLED_1</ffdc>
<ffdc>DCM_INSTALLED_2</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMCINIT_DCM_INSTALL_ERROR</rc>
<description>Error found in DCM installment attribute settings in the PMC INIT phase.</description>
<ffdc>MASTER_TARGET</ffdc>
<ffdc>SLAVE_TARGET</ffdc>
<ffdc>DCM_INSTALLED_1</ffdc>
<ffdc>DCM_INSTALLED_2</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
</hwpError>
</hwpErrors>
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