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<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: src/usr/hwpf/hwp/runtime_errors/p8_pcbs_init_errors.xml $ -->
<!-- -->
<!-- OpenPOWER HostBoot Project -->
<!-- -->
<!-- COPYRIGHT International Business Machines Corp. 2012,2014 -->
<!-- -->
<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
<!-- you may not use this file except in compliance with the License. -->
<!-- You may obtain a copy of the License at -->
<!-- -->
<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
<!-- -->
<!-- Unless required by applicable law or agreed to in writing, software -->
<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
<!-- implied. See the License for the specific language governing -->
<!-- permissions and limitations under the License. -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
<!-- $Id: p8_pcbs_init_errors.xml,v 1.7 2013/12/16 15:28:41 stillgs Exp $ -->
<!-- Error definitions for proc_pcbs_init procedure -->
<hwpErrors>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_PCBS_CODE_SAFE_FSM_TIMEOUT</rc>
<description>Psafe Pstate and FSM-stable timeout in proc_pcbs_init.</description>
<ffdc>LOOPCOUNT</ffdc>
<ffdc>PMSR</ffdc>
<ffdc>PCBSPM_MON1</ffdc>
<ffdc>PCBSPM_MON2</ffdc>
<callout><target>PROC_CHIP</target><priority>HIGH</priority></callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_PCBS_CODE_BAD_MODE</rc>
<description>Unknown mode passed to proc_pcbs_init.</description>
<ffdc>MODE</ffdc>
</hwpError>
<!-- *********************************************************************** -->
</hwpErrors>
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