blob: ba8bd92857ca862db3443b4bb549ed1433a2c72d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
|
<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_slw_base_halt_codes.xml $ -->
<!-- -->
<!-- IBM CONFIDENTIAL -->
<!-- -->
<!-- COPYRIGHT International Business Machines Corp. 2014 -->
<!-- -->
<!-- p1 -->
<!-- -->
<!-- Object Code Only (OCO) source materials -->
<!-- Licensed Internal Code Source Materials -->
<!-- IBM HostBoot Licensed Internal Code -->
<!-- -->
<!-- The source code for this program is not published or otherwise -->
<!-- divested of its trade secrets, irrespective of what has been -->
<!-- deposited with the U.S. Copyright Office. -->
<!-- -->
<!-- Origin: 30 -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
<!-- $Id: proc_slw_base_halt_codes.xml,v 1.9 2013/11/23 00:33:44 cmolsen Exp $ -->
<!-- Halt codes for proc_slw_*.S -->
<hwpErrors>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_UNDEFINED_SV</rc>
<description>
This error is signalled by proc_slw_base and indicates that an
invalid start vector was detected in the EXE_TRIGGER (ETR) register when
kicking off an idle transition. The start vector is in ETR(8:11).
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_PFET_VDD_TIMEOUT_ERROR</rc>
<description>
This error is signalled by proc_slw_poweronoff and indicates that a timeout
occured waiting for the VDD PFET sequencer(s) to complete.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_PFET_VCS_TIMEOUT_ERROR</rc>
<description>
This error is signalled by proc_slw_poweronoff and indicates that a timeout
occured waiting for the VCS PFET sequencer(s) to complete.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_PFET_DECODE_ERROR</rc>
<description>
This error is signalled by proc_slw_poweronoff and indicates that an invalid
PFET decode was detected. This is an SLW firmware issue.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_IVRM_BS_SLEEP_ENTRY_TIMEOUT</rc>
<description>
This error is signalled by proc_slw_base and indicates that a timeout
occured waiting for the internal VRM babystepper to synchronize the idle
transition command during sleep entry.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_IVRM_BS_WINKLE_ENTRY_TIMEOUT</rc>
<description>
This error is signalled by proc_slw_base and indicates that a timeout
occured waiting for the internal VRM babystepper to synchronize the idle
transition command during winkle entry.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_IVRM_BS_EXIT_TIMEOUT</rc>
<description>
This error is signalled by proc_slw_base and indicates that a timeout
occured waiting for the internal VRM babystepper to synchronize the idle
transition command during a fast exit.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_IVRM_CAL_TIMEOUT</rc>
<description>
This error is signalled by proc_slw_base and indicates that a timeout
occured while polling for the iVRM calibration to complete.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_IVRM_CAL_BS_EXIT_TIMEOUT</rc>
<description>
This error is signalled by proc_slw_base and indicates that a timeout
occured waiting for the internal VRM babystepper to synchronize the idle
transition command during a deep exit after iVRM calibration.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_IVRM_FORCESM_TIMEOUT</rc>
<description>
This error is signalled by proc_slw_base and indicates that a timeout
occured waiting for the internal VRM force safe mode to take effect.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_RAM_THREAD_CHECK_ERROR</rc>
<description>
This error is signalled by proc_slw_ram and indicates that a timeout
occured waiting the RAM hardware to accept the instruction given to it..
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_RAM_THREAD_QUIESCE_ERROR</rc>
<description>
This error is signalled by proc_slw_ram and indicates that a timeout
occured waiting the RAM hardware to quiesce.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_RAM_CONTROL_EXCEPTION_ERROR</rc>
<description>
This error is signalled by proc_slw_ram and indicates that RAM controller
indicates recovery is inprogress or an exception has occured..
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_RAM_STATUS_TIMEOUT_ERROR</rc>
<description>
This error is signalled by proc_slw_ram and indicates that a timeout occured
looking for good status from the RAM Controller.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_GOTO_TIMEOUT_ERROR</rc>
<description>
This error is signalled by proc_slw_base and indicates that a timeout occured
looking for the proper PCBS-PM state before issuing a PCBS-PM GOTO command.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_ERRINJ_NEVER_REACH_HALT</rc>
<description>
This error is signalled by proc_slw_pro_epi_log and indicates that the image
updated the PMC status reg but never reached the subsequent halt op. PMC SLW
Timeouts will be indicated without further FIR bits.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_ERRINJ_SIMPLE_HALT</rc>
<description>
This error is signalled by proc_slw_pro_epi_log and indicates that the image
executed the simple halt error injection. PMC SLW Timeouts will be indicated
without further FIR bits.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_ERRINJ_INVALID_INSTR</rc>
<description>
This error is signalled by proc_slw_pro_epi_log and indicates that the image
enabled invalid instruction error injection occured.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_ERRINJ_INVALID_OCI_ADDRESS</rc>
<description>
This error is signalled by proc_slw_pro_epi_log and indicates that the image
enabled invalid OCI address error injection occured.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_ERRINJ_INVALID_PIB_ADDRESS</rc>
<description>
This error is signalled by proc_slw_pro_epi_log and indicates that the image
enabled invalid PIB address error injection occured.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_ERRINJ_PC_UNDERFLOW</rc>
<description>
This error is signalled by proc_slw_pro_epi_log and indicates that the image
enabled PC underflow error injection occured.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_ERRINJ_PC_OVERRFLOW</rc>
<description>
This error is signalled by proc_slw_pro_epi_log and indicates that the image
enabled PC overflow error injection occured.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_ERRINJ_TIMEOUT_ERROR</rc>
<description>
This error is signalled by proc_slw_pro_epi_log and indicates that the image
enabled timeout error injection occured.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_EH_PIB_ERROR</rc>
<description>
This error is signalled by proc_slw_error_handler upon a detected error 0
event (non-masked PIB error code).
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_EH_OCI_ERROR</rc>
<description>
This error is signalled by proc_slw_error_handler upon a detected error 1
event (non-masked OCI error code).
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_EH_INSTRUCTION_ERROR</rc>
<description>
This error is signalled by proc_slw_error_handler upon a detected error 2
event (instruction fetch or decode).
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_EH_INTERNAL_DATA_ERROR</rc>
<description>
This error is signalled by proc_slw_error_handler upon a detected error 3
event (internal data error).
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_EH_ERROR_ON_ERROR</rc>
<description>
This error is signalled by proc_slw_error_handler upon a detected error 4
event (an error was detected upon an error).
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_PMGP1_ENABLE_CONFIG_ERROR</rc>
<description>
This error is signalled by proc_slw_base code when the multicast read AND
and the multicast read OR of the PMGP1 register for the chiplets
represented in the EXE Trigger register do not match. This could be caused
by a configuration error with the Deep Sleep power up and/or down bits or
Deep Winkle power up bit. If these bits match, then a hardware fault is
the next most probable.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>SLW_RC_ILLEGAL_WINKLE_ENTRY_POWER_DOWN</rc>
<description>
This error is signalled by proc_slw_base code (poweronoff portion) and indicates
that the PMGP1 bit for WINKLE_POWER_DOWN when WINKLE_POWER_OFF_SEL is set to 1
(eg a Deep Winkle) has been detected. This is an illegal configuration as it
causes the loss of the High Availability Log Write pointer in the L3 before it
could be saved for restoration upon Deep Winkle Exit.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>SLW_RC_OHA_SPWUP_TIMEOUT</rc>
<description>
This error is signalled by proc_slw_base code when the polling for OHA AISS
achieving the special wake-up state after hitting the PCBS GOTO operation to
complete deep sleep exit.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_SLW_CPM_SPWKUP_NOT_SET</rc>
<description>
This error is signalled by proc_slw_occ_cpm code when it is detected that
special wake-up override isnt enabled which it must be prior to calling
any of the CPM install or enable routines.
</description>
<collectRegisterFfdc>
<id>REG_FFDC_PROC_SLW_REGISTERS</id>
<target>CHIP_IN_ERROR</target>
</collectRegisterFfdc>
<sbeError/>
</hwpError>
<!-- ******************************************************************** -->
</hwpErrors>
|
