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<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: src/usr/hwpf/hwp/p8_fir_registers.xml $ -->
<!-- -->
<!-- OpenPOWER HostBoot Project -->
<!-- -->
<!-- Contributors Listed Below - COPYRIGHT 2014 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
<!-- you may not use this file except in compliance with the License. -->
<!-- You may obtain a copy of the License at -->
<!-- -->
<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
<!-- -->
<!-- Unless required by applicable law or agreed to in writing, software -->
<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
<!-- implied. See the License for the specific language governing -->
<!-- permissions and limitations under the License. -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
<!-- $Id: p8_fir_registers.xml,v 1.3 2014/07/23 19:51:48 jmcgill Exp $ -->
<!-- Definition of FIR registers to collect on some errors -->
<hwpErrors>
<!-- ******************************************************************** -->
<!-- All FIRs *********************************************************** -->
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_PROC_FIR_FFDC</rc>
<description>
FFDC collected on processor FIR errors
</description>
<ffdc>TARGET</ffdc>
<collectRegisterFfdc>
<id>REG_FFDC_CHIP_MASTER_INTERRUPT_REGISTERS</id>
<id>REG_FFDC_CHIP_GLOB_XFIR_REGISTERS</id>
<id>REG_FFDC_CHIP_GLOB_RFIR_REGISTERS</id>
<id>REG_FFDC_CHIP_GLOB_FIR_MASK_REGISTERS</id>
<id>REG_FFDC_CHIP_GLOB_ATTN_REGISTERS</id>
<id>REG_FFDC_CHIP_GLOB_ATTN_MASK_REGISTERS</id>
<id>REG_FFDC_CHIP_LFIR_REGISTERS</id>
<id>REG_FFDC_CHIP_LFIR_MASK_REGISTERS</id>
<target>TARGET</target>
</collectRegisterFfdc>
<collectRegisterFfdc>
<id>REG_FFDC_EX_GLOB_XFIR_REGISTERS</id>
<id>REG_FFDC_EX_GLOB_RFIR_REGISTERS</id>
<id>REG_FFDC_EX_GLOB_FIR_MASK_REGISTERS</id>
<id>REG_FFDC_EX_GLOB_ATTN_REGISTERS</id>
<id>REG_FFDC_EX_GLOB_ATTN_MASK_REGISTERS</id>
<id>REG_FFDC_EX_LFIR_REGISTERS</id>
<id>REG_FFDC_EX_LFIR_MASK_REGISTERS</id>
<childTargets>
<parent>TARGET</parent>
<childType>TARGET_TYPE_EX_CHIPLET</childType>
</childTargets>
</collectRegisterFfdc>
<collectRegisterFfdc>
<id>REG_FFDC_MCS_LFIR_REGISTERS</id>
<id>REG_FFDC_MCS_LFIR_MASK_REGISTERS</id>
<childTargets>
<parent>TARGET</parent>
<childType>TARGET_TYPE_MCS_CHIPLET</childType>
</childTargets>
</collectRegisterFfdc>
<collectRegisterFfdc>
<id>REG_FFDC_XBUS_LFIR_REGISTERS</id>
<id>REG_FFDC_XBUS_LFIR_MASK_REGISTERS</id>
<childTargets>
<parent>TARGET</parent>
<childType>TARGET_TYPE_XBUS_ENDPOINT</childType>
</childTargets>
</collectRegisterFfdc>
<collectRegisterFfdc>
<id>REG_FFDC_ABUS_LFIR_REGISTERS</id>
<id>REG_FFDC_ABUS_LFIR_MASK_REGISTERS</id>
<childTargets>
<parent>TARGET</parent>
<childType>TARGET_TYPE_ABUS_ENDPOINT</childType>
</childTargets>
</collectRegisterFfdc>
</hwpError>
<!-- ******************************************************************** -->
<!-- Chip Level FFDC **************************************************** -->
<!-- ******************************************************************** -->
<registerFfdc>
<id>REG_FFDC_CHIP_MASTER_INTERRUPT_REGISTERS</id>
<cfamRegister>CFAM_FSI_STATUS_0x00001007</cfamRegister>
<scomRegister>MASTER_PCB_INT_0x000F001A</scomRegister>
</registerFfdc>
<!-- ******************************************************************** -->
<registerFfdc>
<id>REG_FFDC_CHIP_GLOB_XFIR_REGISTERS</id>
<scomRegister>READ_GLOBAL_XSTOP_FIR_0x570F001B</scomRegister>
<scomRegister>TP_XSTOP_0x01040000</scomRegister>
<scomRegister>NEST_XSTOP_0x02040000</scomRegister>
<scomRegister>X_XSTOP_0x04040000</scomRegister>
<scomRegister>A_XSTOP_0x08040000</scomRegister>
<scomRegister>PCIE_XSTOP_0x09040000</scomRegister>
<scomRegister>PB_RAS_FIR_0x02010C6E</scomRegister>
</registerFfdc>
<!-- ******************************************************************** -->
<registerFfdc>
<id>REG_FFDC_CHIP_GLOB_RFIR_REGISTERS</id>
<scomRegister>READ_GLOBAL_RECOV_FIR_0x570F001C</scomRegister>
<scomRegister>TP_RECOV_0x01040001</scomRegister>
<scomRegister>NEST_RECOV_0x02040001</scomRegister>
<scomRegister>X_RECOV_0x04040001</scomRegister>
<scomRegister>A_RECOV_0x08040001</scomRegister>
<scomRegister>PCIE_RECOV_0x09040001</scomRegister>
</registerFfdc>
<!-- ******************************************************************** -->
<registerFfdc>
<id>REG_FFDC_CHIP_GLOB_FIR_MASK_REGISTERS</id>
<scomRegister>TP_FIR_MASK_0x01040002</scomRegister>
<scomRegister>NEST_FIR_MASK_0x02040002</scomRegister>
<scomRegister>X_FIR_MASK_0x04040002</scomRegister>
<scomRegister>A_FIR_MASK_0x08040002</scomRegister>
<scomRegister>PCIE_FIR_MASK_0x09040002</scomRegister>
<scomRegister>PB_RAS_FIR_MASK_0x02010C71</scomRegister>
</registerFfdc>
<!-- ******************************************************************** -->
<registerFfdc>
<id>REG_FFDC_CHIP_GLOB_ATTN_REGISTERS</id>
<scomRegister>READ_GLOBAL_SPATT_FIR_0x570F001A</scomRegister>
<scomRegister>TP_SPATTN_0x01040004</scomRegister>
<scomRegister>NEST_SPATTN_0x02040004</scomRegister>
<scomRegister>X_SPATTN_0x04040004</scomRegister>
<scomRegister>A_SPATTN_0x08040004</scomRegister>
<scomRegister>PCIE_SPATTN_0x09040004</scomRegister>
</registerFfdc>
<!-- ******************************************************************** -->
<registerFfdc>
<id>REG_FFDC_CHIP_GLOB_ATTN_MASK_REGISTERS</id>
<scomRegister>TP_SPATTN_MASK_0x01040007</scomRegister>
<scomRegister>NEST_SPATTN_MASK_0x02040007</scomRegister>
<scomRegister>X_SPATTN_MASK_0x04040007</scomRegister>
<scomRegister>A_SPATTN_MASK_0x08040007</scomRegister>
<scomRegister>PCIE_SPATTN_MASK_0x09040007</scomRegister>
</registerFfdc>
<!-- ******************************************************************** -->
<registerFfdc>
<id>REG_FFDC_CHIP_LFIR_REGISTERS</id>
<scomRegister>OCC_LFIR_0x01010800</scomRegister>
<scomRegister>PMC_LFIR_0x01010840</scomRegister>
<scomRegister>OCC_PMC_LFIR_0x01010C00</scomRegister>
<scomRegister>TP_PERV_LFIR_0x0104000A</scomRegister>
<scomRegister>PBA_FIR_0x02010840</scomRegister>
<scomRegister>PSI_HB_FIR_0x02010900</scomRegister>
<scomRegister>HCA_EN_FIR_0x02010940</scomRegister>
<scomRegister>HCA_EN_EHHCA_FIR_0x02010980</scomRegister>
<scomRegister>EN_TPC_INTP_SYNC_FIR_0x020109C0</scomRegister>
<scomRegister>PB_FIR_WEST_0x02010C00</scomRegister>
<scomRegister>PB_FIR_CENT_0x02010C40</scomRegister>
<scomRegister>PB_FIR_EAST_0x02010C80</scomRegister>
<scomRegister>PCIE0_FIR_0x02012000</scomRegister>
<scomRegister>PCIE1_FIR_0x02012400</scomRegister>
<scomRegister>PCIE2_FIR_0x02012800</scomRegister>
<scomRegister>NX_CQ_FIR_0x02013080</scomRegister>
<scomRegister>NX_AS_FIR_0x020130C0</scomRegister>
<scomRegister>NX_DMA_ENG_FIR_0x02013100</scomRegister>
<scomRegister>NX_CAPP_FIR_0x02013000</scomRegister>
<scomRegister>MCD_FIR_0x02013400</scomRegister>
<scomRegister>NEST_PERV_LFIR_0x0204000A</scomRegister>
<scomRegister>PB_X_FIR_0x04010C00</scomRegister>
<scomRegister>X_PSI_FIR_0x04012400</scomRegister>
<scomRegister>X_PERV_LFIR_0x0404000A</scomRegister>
<scomRegister>PB_A_FIR_0x08010800</scomRegister>
<scomRegister>A_PERV_LFIR_0x0804000A</scomRegister>
<scomRegister>ES_PBES_WRAP_TOP_FIR_0x09010800</scomRegister>
<scomRegister>PCIE_IOP0_PLL_FIR_0x09011400</scomRegister>
<scomRegister>PCIE_IOP1_PLL_FIR_0x09011840</scomRegister>
<scomRegister>PCIE_PERV_LFIR_0x0904000A</scomRegister>
</registerFfdc>
<!-- ******************************************************************** -->
<registerFfdc>
<id>REG_FFDC_CHIP_LFIR_MASK_REGISTERS</id>
<scomRegister>OCC_LFIR_MASK_0x01010803</scomRegister>
<scomRegister>PMC_LFIR_MASK_0x01010843</scomRegister>
<scomRegister>OCC_PMC_LFIR_MASK_0x01010C03</scomRegister>
<scomRegister>TP_PERV_LFIR_MASK_0x0104000D</scomRegister>
<scomRegister>PBA_FIR_MASK_0x02010843</scomRegister>
<scomRegister>PSI_HB_FIR_MASK_0x02010903</scomRegister>
<scomRegister>HCA_EN_FIR_MASK_0x02010943</scomRegister>
<scomRegister>HCA_EN_EHHCA_FIR_MASK_0x02010983</scomRegister>
<scomRegister>EN_TPC_INTP_SYNC_FIR_MASK_0x020109C3</scomRegister>
<scomRegister>PB_FIR_MASK_WEST_0x02010C03</scomRegister>
<scomRegister>PB_FIR_MASK_CENT_0x02010C43</scomRegister>
<scomRegister>PB_FIR_MASK_EAST_0x02010C83</scomRegister>
<scomRegister>PCIE0_FIR_MASK_0x02012003</scomRegister>
<scomRegister>PCIE1_FIR_MASK_0x02012403</scomRegister>
<scomRegister>PCIE2_FIR_MASK_0x02012803</scomRegister>
<scomRegister>NX_CQ_FIR_MASK_0x02013083</scomRegister>
<scomRegister>NX_AS_FIR_MASK_0x020130C3</scomRegister>
<scomRegister>NX_DMA_ENG_FIR_MASK_0x02013103</scomRegister>
<scomRegister>NX_CAPP_FIR_MASK_0x02013003</scomRegister>
<scomRegister>MCD_FIR_MASK_0x02013403</scomRegister>
<scomRegister>NEST_PERV_LFIR_MASK_0x0204000D</scomRegister>
<scomRegister>PB_X_FIR_MASK_0x04010C03</scomRegister>
<scomRegister>X_PSI_FIR_MASK_0x04012403</scomRegister>
<scomRegister>X_PERV_LFIR_MASK_0x0404000D</scomRegister>
<scomRegister>PB_A_FIR_MASK_0x08010803</scomRegister>
<scomRegister>A_PERV_LFIR_MASK_0x0804000D</scomRegister>
<scomRegister>ES_PBES_WRAP_TOP_FIR_MASK_0x09010803</scomRegister>
<scomRegister>PCIE_IOP0_PLL_FIR_MASK_0x09011403</scomRegister>
<scomRegister>PCIE_IOP1_PLL_FIR_MASK_0x09011843</scomRegister>
<scomRegister>PCIE_PERV_LFIR_MASK_0x0904000D</scomRegister>
</registerFfdc>
<!-- ******************************************************************** -->
<!-- EX Chiplet Level FFDC ********************************************** -->
<!-- ******************************************************************** -->
<registerFfdc>
<id>REG_FFDC_EX_GLOB_XFIR_REGISTERS</id>
<scomRegister>EX_XSTOP_0x10040000</scomRegister>
</registerFfdc>
<!-- ******************************************************************** -->
<registerFfdc>
<id>REG_FFDC_EX_GLOB_RFIR_REGISTERS</id>
<scomRegister>EX_RECOV_0x10040001</scomRegister>
</registerFfdc>
<!-- ******************************************************************** -->
<registerFfdc>
<id>REG_FFDC_EX_GLOB_FIR_MASK_REGISTERS</id>
<scomRegister>EX_FIR_MASK_0x10040002</scomRegister>
</registerFfdc>
<!-- ******************************************************************** -->
<registerFfdc>
<id>REG_FFDC_EX_GLOB_ATTN_REGISTERS</id>
<scomRegister>EX_SPATTN_0x10040004</scomRegister>
</registerFfdc>
<!-- ******************************************************************** -->
<registerFfdc>
<id>REG_FFDC_EX_GLOB_ATTN_MASK_REGISTERS</id>
<scomRegister>EX_SPATTN_MASK_0x10040007</scomRegister>
</registerFfdc>
<!-- ******************************************************************** -->
<registerFfdc>
<id>REG_FFDC_EX_LFIR_REGISTERS</id>
<scomRegister>EX_CORE_FIR_0x10013100</scomRegister>
<scomRegister>EX_L2_FIR_REG_0x10012800</scomRegister>
<scomRegister>EX_L3_FIR_REG_0x10010800</scomRegister>
<scomRegister>EX_NCU_FIR_REG_0x10010C00</scomRegister>
<scomRegister>EX_PERV_LFIR_0x1004000A</scomRegister>
</registerFfdc>
<!-- ******************************************************************** -->
<registerFfdc>
<id>REG_FFDC_EX_LFIR_MASK_REGISTERS</id>
<scomRegister>EX_CORE_FIR_MASK_0x10013103</scomRegister>
<scomRegister>EX_L2_FIR_MASK_REG_0x10012803</scomRegister>
<scomRegister>EX_L3_FIR_MASK_REG_0x10010803</scomRegister>
<scomRegister>EX_NCU_FIR_MASK_REG_0x10010C03</scomRegister>
<scomRegister>EX_PERV_LFIR_MASK_0x1004000D</scomRegister>
</registerFfdc>
<!-- ******************************************************************** -->
<!-- MCS Chiplet Level FFDC ********************************************* -->
<!-- ******************************************************************** -->
<registerFfdc>
<id>REG_FFDC_MCS_LFIR_REGISTERS</id>
<scomRegister>MCS_MCIFIR_0x02011840</scomRegister>
<scomRegister>IOMC0_BUSCNTL_FIR_0x02011A00</scomRegister>
</registerFfdc>
<!-- ******************************************************************** -->
<registerFfdc>
<id>REG_FFDC_MCS_LFIR_MASK_REGISTERS</id>
<scomRegister>MCS_MCIFIRMASK_0x02011843</scomRegister>
<scomRegister>IOMC0_BUSCNTL_FIR_MASK_0x02011A03</scomRegister>
</registerFfdc>
<!-- ******************************************************************** -->
<!-- XBUS Chiplet Level FFDC ******************************************** -->
<!-- ******************************************************************** -->
<registerFfdc>
<id>REG_FFDC_XBUS_LFIR_REGISTERS</id>
<scomRegister>X_XBUS0_BUSCNTL_FIR_0x04011000</scomRegister>
</registerFfdc>
<!-- ******************************************************************** -->
<registerFfdc>
<id>REG_FFDC_XBUS_LFIR_MASK_REGISTERS</id>
<scomRegister>X_XBUS0_BUSCNTL_FIR_MASK_0x04011003</scomRegister>
</registerFfdc>
<!-- ******************************************************************** -->
<!-- ABUS Chiplet Level FFDC ******************************************** -->
<!-- ******************************************************************** -->
<registerFfdc>
<id>REG_FFDC_ABUS_LFIR_REGISTERS</id>
<scomRegister>A_ABUS_BUSCNTL_FIR_0x08010C00</scomRegister>
</registerFfdc>
<!-- ******************************************************************** -->
<registerFfdc>
<id>REG_FFDC_ABUS_LFIR_MASK_REGISTERS</id>
<scomRegister>A_ABUS_BUSCNTL_FIR_MASK_0x08010C03</scomRegister>
</registerFfdc>
<!-- ******************************************************************** -->
</hwpErrors>
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