path: root/src/usr/hwpf/hwp/memory_attributes.xml

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<!-- $Source: src/usr/hwpf/hwp/memory_attributes.xml $                      -->
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<attributes>
<!-- $Id: memory_attributes.xml,v 1.88 2013/09/04 18:03:12 bellows Exp $ -->
<!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB -->
<!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP -->
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<attribute>
    <id>ATTR_MSS_VOLT</id>
    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
    <description>DRAM Voltage, each voltage rail would need to have a value.  Computed in mss_volt C code - in millivolts
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
</attribute>

<attribute>
    <id>ATTR_MSS_FREQ_OVERRIDE</id>
    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
    <description>FOR LAB USE ONLY: Frequency override of this memory channel in MHz, comprising of up to three DIMMs.  Set by config file or an attribute writing program.  Consumed by mss_freq.  The default of AUTO means mss_freq will find the best frequencies given the DIMMs plugged in and other rules.  Otherwise, this is the system frequency.
firmware notes: Platforms should initialize this attribute to AUTO (0)</description>
    <valueType>uint32</valueType>
    <enum>AUTO = 0</enum>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_MSS_FREQ</id>
    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
    <description>Frequency of this memory channel in MHz, comprising of three DIMMs.  Computed in mss_freq
creator: mss_freq
consumer: mss_eff_cnfg, others
firmware notes: none</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_FREQ_BIAS_PERCENTAGE</id>
    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
    <description>Percentage to increase/decrease MEM frequency - two's complement number.  Measured in 100's.  So the value of 100 is one percent increase.
This frequency change comes from changing multipliers and dividers to  get the desired frequency.  The supported frequencies come from Tim Diemoz.
Creator: platform set this to 0.  Users can set this to a valid value.
VALID Values: (TBD % to TBD %) (Tuleta) (TBD % to TBD %) (Glacier)
Set by: PLL settings written by Dave Cadigan</description>
    <valueType>uint32</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_DIMM_MFG_ID_CODE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Manufacturer ID Code RCD: bits(31:16), Module: bits(15:0)</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_DIMM_RANKS_CONFIGED</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Bit wise representation of master ranks in each DIMM that are used for reads and writes. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
Dimensions are [port][dimm]  A/B=Mba_0 C/D=Mba_1 There are only two DIMM ranks: DIMM0 and DIMM1 where DIMM0 is the furthest from the centaur.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_EFF_NUM_RANKS_PER_DIMM</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Number of ranks in each DIMM. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
values are 0,1,2, 4 up to 32
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_EFF_DIMM_TYPE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Type of DIMM: RDIMM, UDIMM, LRDIMM as specified by the JEDIC standard. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
NOTE: Do not use the enum type of CDIMM.  Use the attribute EFF_DIMM_CUSTOM to test for a CUSTOM DIMM or CDIMM.</description>
    <valueType>uint8</valueType>
    <enum>CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_EFF_CUSTOM_DIMM</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>DIMM is a custom DIMM. This is commonly known as a CDIMM, but technically, we could support Custom DIMMs of different types than an UDIMM, such as RDIMM and LRDIMM.  Created in mss_eff_cnfg
Use this attribute if you need to know if the Centaur is on the DIMM instead of on a planar.</description>
    <valueType>uint8</valueType>
    <enum>NO = 0, YES = 1</enum>
    <platActionWrite/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_WIDTH</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>DRAM Device Width: X4, X8, X16, X32. Used in various locations and is computed in mss_eff_cnfg.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>X4 = 4, X8 = 8, X16 = 16, X32 = 32</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_GEN</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Generation of memory: DDR3, DDR4. Used in various locations and is computed in mss_eff_cnfg.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>EMPTY = 0, DDR3 = 1, DDR4 = 2</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_PRIMARY_RANK_GROUP0</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>INVALID = 255</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_PRIMARY_RANK_GROUP1</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>INVALID = 255</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_PRIMARY_RANK_GROUP2</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>INVALID = 255</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_PRIMARY_RANK_GROUP3</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>INVALID = 255</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_SECONDARY_RANK_GROUP0</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>INVALID = 255</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_SECONDARY_RANK_GROUP1</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>INVALID = 255</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_SECONDARY_RANK_GROUP2</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>INVALID = 255</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_SECONDARY_RANK_GROUP3</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>INVALID = 255</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_TERTIARY_RANK_GROUP0</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>INVALID = 255</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_TERTIARY_RANK_GROUP1</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>INVALID = 255</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_TERTIARY_RANK_GROUP2</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>INVALID = 255</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_TERTIARY_RANK_GROUP3</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>INVALID = 255</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_QUATERNARY_RANK_GROUP0</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>INVALID = 255</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_QUATERNARY_RANK_GROUP1</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>INVALID = 255</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_QUATERNARY_RANK_GROUP2</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>INVALID = 255</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_QUATERNARY_RANK_GROUP3</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>INVALID = 255</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_ODT_RD</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Read ODT. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: VPD(MT),mss_eff_cnfg_termination
consumer: various.C files and initfiles
firmware notes: none</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2 4</array>
</attribute>

<attribute>
    <id>ATTR_EFF_ODT_WR</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Write ODT. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
Creator: VPD(MT)/ mss_eff_cnfg_termination
consumer: various.C and initfile
firmware notes: none</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2 4</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CKE_MAP</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Rank to CKE map. Used in various locations and is computed in mss_eff_cnfg_cke_map. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.   creator: mss_eff_cnfg_cke_map consumer: various firmware notes: none - NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2 4</array>
</attribute>

<attribute>
    <id>ATTR_EFF_SPCKE_MAP</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Rank to Spare CKE map. Used in various locations and is computed in mss_eff_cnfg_cke_map. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.   creator: mss_eff_cnfg_cke_map consumer: various firmware notes: none NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2 4</array>
</attribute>

<attribute>
    <id>ATTR_EFF_DIMM_SPARE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Spare DRAM availability. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.   creator: mss_eff_cnfg consumer: various firmware notes: load from spd</description>
    <valueType>uint8</valueType>
    <enum>NO_SPARE = 0, LOW_NIBBLE = 1, HIGH_NIBBLE = 2, FULL_BYTE = 3</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2 4</array>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_RON</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>DRAM Ron. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
OHM48 is for DDR4.
creator: VPD(MT)/mss_eff_cnfg_termination
consumer: various.C files (no initfile)
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>OHM34 = 34, OHM40 = 40, OHM48 = 48</enum>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_RTT_NOM</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>DRAM Rtt_Nom. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: VPD(MT),mss_eff_cnfg_termination
consumer: various.C files (no initfiles)
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>DISABLE = 0, OHM20 = 20, OHM30 = 30, OHM34 = 34, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM240 = 240</enum>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2 4</array>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_RTT_WR</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>DRAM Rtt_WR. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
Creator: VPD(MT), mss_eff_cnfg_termination
consumer: various.C files (no initfiles)
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>DISABLE = 0, OHM60 = 60, OHM120 = 120, OHM240 = 240, HIGHZ = 1</enum>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2 4</array>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_WR_VREF</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>DRAM Write Vref. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: VPD(MT) or mss_eff_cnfg_termination
consumer: various.C and initfile
firmware notes: none
This is the nominal value
This is for DDR3</description>
    <valueType>uint32</valueType>
    <enum>VDD420 = 420, VDD425 = 425, VDD430 = 430, VDD435 = 435, VDD440 = 440, VDD445 = 445, VDD450 = 450, VDD455 = 455, VDD460 = 460, VDD465 = 465, VDD470 = 470, VDD475 = 475, VDD480 = 480, VDD485 = 485, VDD490 = 490, VDD495 = 495, VDD500 = 500, VDD505 = 505, VDD510 = 510, VDD515 = 515, VDD520 = 520, VDD525 = 525, VDD530 = 530, VDD535 = 535, VDD540 = 540, VDD545 = 545, VDD550 = 550, VDD555 = 555, VDD560 = 560, VDD565 = 565, VDD570 = 570, VDD575 = 575</enum>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_WRDDR4_VREF</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>DRAM Write Vref. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: VPD(MT) or mss_eff_cnfg_termination
consumer: various
firmware notes: none
This is the nominal value
This is for DDR4
The value is from 0 to 50</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_WR_VREF_SCHMOO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Enables for which VREF to use on the WR Schmoo.  The LSB corresponds to the highest WR Vref</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_WRDDR4_VREF_SCHMOO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Enables for which VREF to use on the WR Schmoo.  The LSB corresponds to the highest WR Vref</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_DRV_IMP_DQ_DQS</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Centaur DQ and DQS Drive Impedance Used in various locations and comes from the MT Keyword of the VPD or  is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: VPD(MT)/mss_eff_cnfg_termination
consumer: initfile,various.C files
firmware notes: none
This is the nominal value</description>
    <valueType>uint8</valueType>
    <enum>OHM24_FFE0, OHM30_FFE0,
OHM30_FFE480, OHM30_FFE240, OHM30_FFE160, OHM30_FFE120, OHM34_FFE0, OHM34_FFE480, OHM34_FFE240, OHM34_FFE160, OHM34_FFE120, OHM40_FFE0, OHM40_FFE480, OHM40_FFE240, OHM40_FFE160, OHM40_FFE120</enum>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_DRV_IMP_ADDR</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Centaur Address Drive Impedance Used in various locations and comes from the MT keyword of the VPD or  is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_termination
consumer: initfile and various.C
firmware notes: none
This is the nominal value</description>
    <valueType>uint8</valueType>
    <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40</enum>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_DRV_IMP_CNTL</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Centaur Control Drive Impedance Used in various locations and comes from the MT keyword of the VPD or  is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: VPD(MT)/mss_eff_cnfg_termination
consumer: initfile,various .C
firmware notes: none
This is the nominal value</description>
    <valueType>uint8</valueType>
    <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40</enum>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_DRV_IMP_CLK</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Centaur Clock Drive Impedance Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: VPD(MT),mss_eff_cnfg_termination
consumer: initfiles,various
firmware notes: none
This is the nominal value</description>
    <valueType>uint8</valueType>
    <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40</enum>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_DRV_IMP_SPCKE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Centaur Spare Clock Drive Impedance Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: VPD(MT) , mss_eff_cnfg_termination
consumer: initfiles, various.C
firmware notes: none
This is the nominal value</description>
    <valueType>uint8</valueType>
    <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40</enum>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Enables for which impedance values can be used and tested in a timing test.  The bits have a one to one correspondence to the possible driver strengths and start with the first value down to the last (largest) impedance as the LSB of the 8 bit field.</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_DRV_IMP_CLK_SCHMOO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Enables for which impedance values can be used and tested in a timing test.  The bits have a one to one correspondence to the possible driver strengths and start with the first value down to the last (largest) impedance as the LSB of the 8 bit field.</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_DRV_IMP_SPCKE_SCHMOO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Enables for which impedance values can be used and tested in a timing test.  The bits have a one to one correspondence to the possible driver strengths and start with the first value down to the last (largest) impedance as the LSB of the 8 bit field.</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_DRV_IMP_CNTL_SCHMOO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Enables for which impedance values can be used and tested in a timing test.  The bits have a one to one correspondence to the possible driver strengths and start with the first value down to the last (largest) impedance as the LSB of the 8 bit field.
This is the nominal value</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_RCV_IMP_DQ_DQS</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Centaur DQ and DQS Receiver Impedance Used in various locations and it comes from the VPD MT keyword for custom DIMMs or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: VPD, mss_eff_cnfg_termination
Consumer: initfile + C code
firmware notes: none
This is the nominal value</description>
    <valueType>uint8</valueType>
    <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40, OHM48 = 48, OHM60 = 60,  OHM80 = 80, OHM120 = 120, OHM160 = 160, OHM240 = 240</enum>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Enables for which impedance values can be used and tested in a timing test.  The bits have a one to one correspondence to the possible receiver termination and start with the first value down to the last (largest) impedance as the LSB of the 32 bit field.</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_SLEW_RATE_DQ_DQS</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Centaur DQ and DQS Slew Rate Used in various locations and comes from the MT keyword of the VPD or  is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: VPD(MT), mss_eff_cnfg_termination
consumer: initfiles,various.C
firmware notes: none
This is the nominal value</description>
    <valueType>uint8</valueType>
    <enum>SLEW_3V_NS = 3,
SLEW_4V_NS = 4,
SLEW_5V_NS = 5,
SLEW_6V_NS = 6,
SLEW_MAXV_NS = 7</enum>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_SLEW_RATE_ADDR</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Centaur Address Slew Rate Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: VPD(MT),mss_eff_cnfg_termination
consumer: initfile,various .C files
firmware notes: none
This is the nominal value</description>
    <valueType>uint8</valueType>
    <enum>SLEW_3V_NS = 3,
SLEW_4V_NS = 4,
SLEW_5V_NS = 5,
SLEW_6V_NS = 6,
SLEW_MAXV_NS = 7</enum>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_SLEW_RATE_CLK</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Centaur Clock Slew Rate Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: VPD(MT)mss_eff_cnfg_termination
consumer: initfile,various.C files
firmware notes: none
This is the nominal value</description>
    <valueType>uint8</valueType>
    <enum>SLEW_3V_NS = 3,
SLEW_4V_NS = 4,
SLEW_5V_NS = 5,
SLEW_6V_NS = 6,
SLEW_MAXV_NS = 7</enum>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_SLEW_RATE_SPCKE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Centaur Spare Clock Slew Rate Used in various locations and comes from the MT keyword or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: VPD(MT) or mss_eff_cnfg_termination
consumer: initfile,various.C
firmware notes: none
This is the nominal value</description>
    <valueType>uint8</valueType>
    <enum>SLEW_3V_NS = 3,
SLEW_4V_NS = 4,
SLEW_5V_NS = 5,
SLEW_6V_NS = 6,
SLEW_MAXV_NS = 7
</enum>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_SLEW_RATE_CNTL</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Centaur Control Slew Rate Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: VPD(MT),mss_eff_cnfg_termination
consumer:initfile, various .C files
firmware notes: none
This is the nominal value</description>
    <valueType>uint8</valueType>
    <enum>SLEW_3V_NS = 3,
SLEW_4V_NS = 4,
SLEW_5V_NS = 5,
SLEW_6V_NS = 6,
SLEW_MAXV_NS = 7
</enum>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Slew Rates that can be selected during timing adjustments.  The fastest rate is the LSB</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_SLEW_RATE_CLK_SCHMOO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Slew Rates that can be selected during timing adjustments.  The fastest rate is the LSB</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_SLEW_RATE_SPCKE_SCHMOO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Slew Rates that can be selected during timing adjustments.  The fastest rate is the LSB</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_SLEW_RATE_ADDR_SCHMOO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Slew Rates that can be selected during timing adjustments.  The fastest rate is the LSB</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_SLEW_RATE_CNTL_SCHMOO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Slew Rates that can be selected during timing adjustments.  The fastest rate is the LSB</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_RD_VREF</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Centaur Read Vref. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
Creator: VPD(MT) or mss_eff_cnfg_termination
consumer: various.C and initfiles
firmware notes: none
This is the nominal value</description>
    <valueType>uint32</valueType>
    <enum>VDD40375 = 40375, VDD41750 = 41750, VDD43125 = 43125, VDD44500 = 44500, VDD45875 = 45875, VDD47250 = 47250, VDD48625 = 48625, VDD50000 = 50000, VDD51375 = 51375, VDD52750 = 52750, VDD54125 = 54125, VDD55500 = 55500, VDD56875 = 56875, VDD58250 = 58250, VDD59625 = 59625, VDD61000 = 61000, VDD60375 = 60375, VDD61750 = 61750, VDD63125 = 63125, VDD64500 = 64500, VDD65875 = 65875, VDD67250 = 67250, VDD68625 = 68625, VDD70000 = 70000, VDD71375 = 71375, VDD72750 = 72750, VDD74125 = 74125, VDD75500 = 75500, VDD76875 = 76875, VDD78250 = 78250, VDD79625 = 79625, VDD81000 = 81000</enum>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_RD_VREF_SCHMOO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Enables for which VREF value can be used in timing adjustments.  The highest voltage corresponds to the LSB</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_DIMM_SIZE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>DIMM Size.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_BANKS</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Number of DRAM banks.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_ROWS</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Number of DRAM rows.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_COLS</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Number of DRAM columns.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_DENSITY</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>DRAM Density.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_TRCD</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RAS to CAS Delay.  Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_TRRD</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Row ACT to Row ACT Delay.  Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_TRP</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Row Precharge Delay.  Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_TRAS</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>ACT to Precharge Delay.  Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_TRC</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>ACT to ACT/Refresh Delay.  Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_TRFI</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Refresh Interval. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  In unit clock.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_TRFC</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Refresh Recovery Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  In unit clock.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_TWTR</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Internal Write to Read Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_TRTP</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Internal Read to Precharge Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_TFAW</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Four ACT Window Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_BL</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Burst Length.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>BL8 = 0, OTF = 1, BC4 = 2</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_CL</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>CAS Latency.  Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_AL</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Additive Latency.  Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>DISABLE = 0, CL_MINUS_1 = 1, CL_MINUS_2 = 2</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_CWL</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>CAS Write Latency.  Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_RBT</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Read Burst Type.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>SEQUENTIAL = 0, INTERLEAVE = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_TM</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Test Mode.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>NORMAL= 0, TEST = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_DLL_RESET</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>DLL Reset.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>NO = 0, YES = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_WR</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Write Recovery.  Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_DLL_PPD</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>DLL Precharge PD.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>SLOWEXIT = 0, FASTEXIT = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_DLL_ENABLE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>DLL Enable.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>ENABLE = 0, DISABLE = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_TDQS</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>TDQS. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>DISABLE = 0, ENABLE = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_WR_LVL_ENABLE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Write Level Enable. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>DISABLE = 0, ENABLE = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_OUTPUT_BUFFER</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>DRAM Qoff. Enables or disables DRAM output. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>ENABLE = 0, DISABLE = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_PASR</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Partial Array Self-Refresh. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>FULL = 0, FIRST_HALF = 1, FIRST_QUARTER = 2, FIRST_EIGHTH = 3, LAST_THREE_FOURTH = 4, LAST_HALF = 5, LAST_QUARTER = 6, LAST_EIGHTH = 7</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_ASR</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Auto Self-Refresh. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>SRT = 0, ASR = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_SRT</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Self-Refresh Temperature Range. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>NORMAL = 0, EXTEND = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_MPR_LOC</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Multi Purpose Register Location. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_MPR_MODE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Multi Purpose Register Mode. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>DISABLE = 0, ENABLE = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RCD Control Word. Used in mss_dram_init and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none</description>
    <valueType>uint64</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_DIMM_RCD_IBT</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RCD IBT. Used in mss_dram_init and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none</description>
    <valueType>uint32</valueType>
    <enum>IBT_OFF = 0, IBT_100 = 100, IBT_150 = 150, IBT_200 = 200, IBT_300 = 300</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_DIMM_RCD_MIRROR_MODE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RCD IBT. Used in mss_dram_init and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>IBT_BACK_OFF = 0, IBT_BACK_ON = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_SCHMOO_MODE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Specifies the schmoo mode to use during draminit_train_adv.</description>
    <valueType>uint8</valueType>
    <enum>FAST = 0, ONE_SLOW = 1, QUARTER_SLOW = 2, HALF_SLOW = 3, FULL_SLOW = 4, ONE_CHAR = 5, QUARTER_CHAR = 6, HALF_CHAR = 7, FULL_CHAR = 8</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_SCHMOO_ADDR_MODE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Specifies the schmoo mode to use during draminit_train_adv</description>
    <valueType>uint8</valueType>
    <enum>FEW_ADDR= 0, QUARTER_ADDR = 1, HALF_ADDR = 2, FULL_ADDR = 3</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_SCHMOO_TEST_VALID</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Specifies the schmoo test to run during draminit_train_adv. Bit wise.</description>
    <valueType>uint8</valueType>
    <enum> NONE = 0x00,
 MCBIST = 0x01,
 WR_EYE = 0x02,
 RD_EYE = 0x04,
 WR_DQS = 0x08,
 RD_DQS = 0x10</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_SCHMOO_PARAM_VALID</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Specifies the schmoo parameters to use during draminit_train_adv. Bit wise.</description>
    <valueType>uint8</valueType>
    <enum> PARAM_NONE = 0x00,
 DELAY_REG = 0x01,
 DRV_IMP = 0x02,
 SLEW_RATE = 0x04,
 WR_VREF = 0x08,
 RD_VREF = 0x10,
 RCV_IMP = 0x20</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_SCHMOO_WR_EYE_MIN_MARGIN</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_SCHMOO_RD_EYE_MIN_MARGIN</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_SCHMOO_DQS_CLK_MIN_MARGIN</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_SCHMOO_RD_GATE_MIN_MARGIN</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_SCHMOO_ADDR_CMD_MIN_MARGIN</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_MEMCAL_INTERVAL</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Specifies the memcal interval in clocks.</description>
    <valueType>uint32</valueType>
    <enum>DISABLE = 0</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_ZQCAL_INTERVAL</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Specifies the zqcal interval in clocks.</description>
    <valueType>uint32</valueType>
    <enum>DISABLE = 0</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_IBM_TYPE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Specifies the memory topology type. See centaur workbook.</description>
    <valueType>uint8</valueType>
    <enum>UNDEFINED = 0, TYPE_1A = 1, TYPE_1B = 2, TYPE_1C = 3, TYPE_1D = 4, TYPE_2A = 5, TYPE_2B = 6, TYPE_2C = 7, TYPE_3A = 8, TYPE_3B = 9, TYPE_3C = 10, TYPE_4A = 11, TYPE_4B = 12, TYPE_4C = 13, TYPE_5A = 14, TYPE_5B = 15, TYPE_5C = 16, TYPE_5D = 17, TYPE_6A = 18, TYPE_6B = 19, TYPE_6C = 20, TYPE_7A = 21, TYPE_7B = 22, TYPE_7C = 23, TYPE_8A = 24, TYPE_8B = 25, TYPE_8C = 26</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_NUM_DROPS_PER_PORT</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Specifies the number of DIMM dimensions that are valid per port. </description>
    <valueType>uint8</valueType>
    <enum>EMPTY = 0, SINGLE = 1, DUAL = 2</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_STACK_TYPE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Specifies the DRAM package type.</description>
    <valueType>uint8</valueType>
    <enum>NONE = 0, DDP_QDP = 1, STACK_3DS = 2</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Specifies the number of master ranks per DIMM.</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_NUM_PACKAGES_PER_RANK</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Specifies the number of DRAM packages per rank.</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_NUM_DIES_PER_PACKAGE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Specifies the number of DRAM dies per package.</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
</attribute>

<attribute>
    <id>ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>This is the throttle numerator setting for cfg_nm_n_per_mba creator: mss_eff_cnfg consumer: mc_config firmware notes: none</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_MEM_THROTTLE_DENOMINATOR</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>This is the throttle denominator setting for cfg_nm_m creator: mss_eff_cnfg consumer: mc_config  firmware notes: none</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>This is the throttle numerator setting for cfg_nm_n_per_chip creator: mss_eff_cnfg consumer: mc_config firmware notes: none</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_MEM_WATT_TARGET</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Total memory power limit in cW for the dimms on the memory channel pair. Used to compute the throttles on the channel and/or dimms creator: unknown consumer: mss_eff_config firmware notes: none</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_POWER_SLOPE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Master Power slope value for dimm</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_POWER_SLOPE2</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Supplier Power slope value for dimm</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_POWER_INT</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Master Power intercept value for dimm</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_POWER_INT2</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Supplier Power intercept value for dimm</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_DIMM_MAXBANDWIDTH_GBS</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>DIMM Max Bandwidth in GBs output from thermal procedures</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_DIMM_MAXBANDWIDTH_MRS</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>DIMM Max Bandwidth in MRs output from thermal procedures</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_CHANNEL_MAXBANDWIDTH_GBS</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Channel Max Bandwidth in GBs output from thermal procedures</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_CHANNEL_PAIR_MAXBANDWIDTH_GBS</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Channel Pair Max Bandwidth in GBs output from thermal procedures</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_CHANNEL_MAXBANDWIDTH_MRS</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Channel Max Bandwidth MRs output from thermal procedures</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_CHANNEL_PAIR_MAXBANDWIDTH_MRS</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Channel Pair Max Bandwidth MRs output from thermal procedures</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_DIMM_MAXPOWER</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>DIMM Max Power output from thermal procedures</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_CHANNEL_MAXPOWER</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Channel Max Power output from thermal procedures</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_CHANNEL_PAIR_MAXPOWER</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Channel Pair Max Power output from thermal procedures</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Runtime throttle numerator setting for cfg_nm_n_per_mba</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Runtime throttle denominator setting for cfg_nm_m</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Runtime throttle numerator setting for cfg_nm_n_per_chip</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>Machine Readable Workbook safe mode throttle value for numerator cfg_nm_n_per_mba</description>
    <valueType>uint32</valueType>
    <platInit/>
    <odmVisable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MRW_SAFEMODE_MEM_THROTTLE_DENOMINATOR</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>Machine Readable Workbook safe mode throttle value for denominator cfg_nm_m</description>
    <valueType>uint32</valueType>
    <platInit/>
    <odmVisable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>Machine Readable Workbook safe mode throttle value for numerator cfg_nm_n_per_chip</description>
    <valueType>uint32</valueType>
    <platInit/>
    <odmVisable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MRW_THERMAL_MEMORY_POWER_LIMIT</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>Machine Readable Workbook Thermal Memory Power Limit</description>
    <valueType>uint32</valueType>
    <platInit/>
    <odmVisable/>
</attribute>

<attribute>
    <id>ATTR_MSS_INTERLEAVE_ENABLE</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>Used in the setting of groups.  It is a bit vector.  If the value  BITWISE_AND  1 = 1 then groups of 1 are enabled with special checkerboard modes needed, if the value  BITWISE_AND  2 = 2, then groups of 2 are possible; if value  BITWISE_AND  4, the groups of 4 are possible; if value  BITWISE_AND  8, the groups of 8 are possible.  If no groups can formed according to this input, then an error will be thrown.</description>
    <valueType>uint8</valueType>
    <platInit/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>This dial sets the Centaur address bits used to interleave addresses between MBA01 and MBA23.  Valid values are 23 through 32.  See Centaur Spec Chapter 5 for details.   Used in the intifile </description>
    <valueType>uint8</valueType>
    <platInit/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>Value of on or off.  On is 256 bit interleave.  Off, the translation is on 128  bit interleave mode.  See centaur workbook chapter 5.</description>
    <valueType>uint8</valueType>
    <enum>OFF = 0, ON = 1</enum>
    <platInit/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_MSS_CACHE_ENABLE</id>
    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
    <description>Reflects the functionality of the L4 Cache.  Determines if the L4 is enabled or not. See chapter 6 of the Centaur Workbook.  On means the full cache is enabled.  HALF_A (EVEN) means only A is enabled and HALF_B (ODD) means only B is enabled. For DD1X, the values of UNK_OFF, UNK_ON, UNK_HALF_A and UNK_HALFB were added because early parts did not have the fuses blown correctly, so the cache repairs may not have worked. This value is set by the platform which can get the chips value by running the mss_cen_get_ecid function.
Note: Cronus and Firmware plus our initfiles do not really support any of the UNK values.  It is the responsibility of the platform to map the UNK values to the appropriate value of OFF/ON/HALF_A/HALF_B</description>
    <valueType>uint8</valueType>
    <enum>OFF = 0, ON = 1, HALF_A = 3, HALF_B = 5, UNK_OFF = 8, UNK_ON = 9, UNK_HALF_A = 0xB, UNK_HALF_B = 0xD</enum>
    <platInit/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_MSS_PREFETCH_ENABLE</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>Value of on or off.  Determines if prefetching enabled or not. See chapter 7 of the Centaur Workbook.</description>
    <valueType>uint8</valueType>
    <enum>OFF = 0, ON = 1</enum>
    <platInit/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_MSS_CLEANER_ENABLE</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>Value of on or off.  Determines if the cleaner of the L4 cache (write modified entries to memory on idle cycles)  enabled or not. See chapter 7 of the Centaur Workbook.</description>
    <valueType>uint8</valueType>
    <enum>OFF = 0, ON = 1</enum>
    <platInit/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_MSS_LAB_OVERRIDE_FOR_MEM_PLL</id>
    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
    <description>Tell the cen_mem_pll_setup procedure to override the default Centaur MEM PLL settings with user-specified scan chain data.
creator: lab user
consumer: cen_mem_pll_setup
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
</attribute>

<attribute>
    <id>ATTR_MSS_MEM_MC_IN_GROUP</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>A 8 bit vector that would be a designation of which MC are involved in the group. So the bits would represent MC0,MC1,MC2,MC3,MC4,MC5,MC6,MC7-what is grouped into the first would go into [0], the 2nd group into entry [1] and so on. set in the mss_setup_bars</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array>8</array>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_MCS_GROUP_32</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>Data Structure from eff grouping to setup bars to help determine different groups
   Non- Mirroring [0-7] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
 //  Mirroring      [8-15] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
Measured in GB</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array>16 16</array>
</attribute>

<attribute>
    <id>ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>A bit vector (per Dean's request) specifying if a DIMM is functional.  DIMM attributes, such as SIZE, are qualified by this bit vector.  The attribute ANDed 0x80 means port 0, DIMM 0 is functional, 0x40 means port 0, DIMM 1 is functional.  0x08 means port 1, DIMM 0 is functional and 0x04 means port 1 DIMM 1 is functional.  A fully populated system would have the value of 0xCC. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none
This factors in functionality</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_LPASR</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description> Low Power Auto Self-Refresh. This is for DDR4 MRS2.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>MANUAL_NORMAL =0, MANUAL_REDUCED = 1, MANUAL_EXTENDED = 2, ASR = 3</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_MPR_PAGE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>MPR Page Selection This is for DDR4 MRS3.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_GEARDOWN_MODE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Gear Down Mode. This is for DDR4 MRS3.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>HALF =0, QUARTER=1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_PER_DRAM_ACCESS</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Per DRAM accessibility.  This is for DDR4 MRS3.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>ENABLE = 0, DISABLE = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_TEMP_READOUT</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Temperature sensor readout. This is for DDR4 MRS3.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>ENABLE = 0, DISABLE = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_FINE_REFRESH_MODE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Fine refresh mode. This is for DDR4 MRS3.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>FIXED_2X = 0, FIXED_4X = 1, FLY_2X = 2, FLY_4X = 3, NORMAL = 4</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_CRC_WR_LATENCY</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>write latency for CRC and DM. This is for DDR4 MRS3.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>4NCK = 0, 5NCK = 2, 6NCK = 3</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_MPR_RD_FORMAT</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>MPR READ FORMAT. This is for DDR4 MRS3.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>SERIAL = 0, PARALLEL = 1, STAGGERED = 2, RESERVED_TEMP= 3</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_MAX_POWERDOWN_MODE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Max Power down mode. This is for DDR4 MRS4.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>ENABLE = 0, DISABLE = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_TEMP_REF_RANGE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Temp ref range. This is for DDR4 MRS4.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>NORMAL = 0, EXTEND = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_TEMP_REF_MODE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Temp controlled ref mode. This is for DDR4 MRS4.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>ENABLE = 0, DISABLE = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_INT_VREF_MON</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Internal Vref Monitor.. This is for DDR4 MRS4.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>ENABLE = 0, DISABLE = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_CS_CMD_LATENCY</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>CS to CMD/ADDR Latency. This is for DDR4 MRS4.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_SELF_REF_ABORT</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Self Refresh Abort. This is for DDR4 MRS4.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>ENABLE = 0, DISABLE = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_RD_PREAMBLE_TRAIN</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Read Pre amble Training Mode. This is for DDR4 MRS4.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>ENABLE = 0, DISABLE = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_RD_PREAMBLE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Read Pre amble. This is for DDR4 MRS4.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>1NCLK = 0, 2NCLK = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_WR_PREAMBLE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Write Pre amble. This is for DDR4 MRS4.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>1NCLK = 0, 2NCLK = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_CA_PARITY_LATENCY</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>C/A Parity Latency Mode. This is for DDR4 MRS5.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>DISABLE = 0</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_CRC_ERROR_CLEAR</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>CRC Error Clear. This is for DDR4 MRS5.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>ERROR = 0, CLEAR = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_CA_PARITY_ERROR_STATUS</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>C/A Parity Error Status. This is for DDR4 MRS5.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>ERROR = 0, CLEAR = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_ODT_INPUT_BUFF</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>ODT Input Buffer during power down. This is for DDR4 MRS5.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>ACTIVATED = 0, DEACTIVATED = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_RTT_PARK</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RTT_Park value. This is for DDR4 MRS5.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>DISABLE = 0, 60OHM = 1, 40OHM = 2, 120OHM = 3, 240OHM = 4, 48OHM = 5, 80OHM = 6, 34OHM = 7</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2 4</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CA_PARITY</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>CA Parity Persistance Error. This is for DDR4 MRS5.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>ENABLE = 0, DISABLE = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DATA_MASK</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Data Mask. This is for DDR4 MRS5.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>DISABLE = 0, ENABLE = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_WRITE_DBI</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Write DBI. This is for DDR4 MRS5.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>DISABLE = 0, ENABLE = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_READ_DBI</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Read DBI. This is for DDR4 MRS5.  Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>DISABLE = 0, ENABLE = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_VREF_DQ_TRAIN_VALUE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>vrefdq_train value. This is for DDR4 MRS6.  Computed in mss_eff_cnfg. Each memory channel will have a value.
Creator: mss_eff_cnfg
Consumer:various
Firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2 4</array>
</attribute>

<attribute>
    <id>ATTR_VREF_DQ_TRAIN_RANGE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>vrefdq_train range. This is for DDR4 MRS6.  Computed in mss_eff_cnfg. Each memory channel will have a value.
Creator: mss_eff_cnfg
Consumer:various
Firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>RANGE1 = 0, RANGE2 = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2 4</array>
</attribute>

<attribute>
    <id>ATTR_VREF_DQ_TRAIN_ENABLE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>vrefdq_train enable. This is for DDR4 MRS6.  Computed in mss_eff_cnfg. Each memory channel will have a value.
Creator: mss_eff_cnfg
Consumer:various
Firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>ENABLE = 0, DISABLE = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2 4</array>
</attribute>

<attribute>
    <id>ATTR_TCCD_L</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>tccd_l. This is for DDR4 MRS6.  Computed in mss_eff_cnfg. Each memory channel will have a value.
Creator: mss_eff_cnfg
Consumer:various
Firmware notes: none</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_WRITE_CRC</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Write CRC control for DDR4.  Set in mss_eff_cnfg.  Each memory channel will have a value.
Creator: mss_eff_cnfg
Consumer:various
Firmware notes: none</description>
    <valueType>uint8</valueType>
    <enum>ENABLE = 0, DISABLE = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_MSS_CAL_STEP_ENABLE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>A bit vector denoting valid cal steps to run during dram_init_train. [0] EXT_ZQCAL
[1] WR_LEVEL
[2] DQS_ALIGN
[3] RDCLK_ALIGN
[4] READ_CTR
[5] WRITE_CTR
[6] COARSE_WR
[7] COARSE_RD
bits6:7  will be consumed together to form COARSE_LVL. </description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_MEM_IPL_COMPLETE</id>
    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    <description>A numerical number indicating if the memory procedures are complete.  written by mss_setup_bars when the bars are now functional in the processor.  </description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_MSS_SLEW_RATE_DATA</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>The 4 bit result of running the slew calibration algorithm at various rates and impedances.  The first dimension is port, the second is the impedance of 24,30,34, and 40 Ohms.  The 3rd dimension is the rate: 3,4,5 or 6 V/ns.  Computed and sent to the correct data blocks in phy_reset.  Also used in advanced training</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 4 4</array>
</attribute>

<attribute>
    <id>ATTR_MSS_SLEW_RATE_ADR</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>The 4 bit result of running the slew calibration algorithm at various rates and impedances.  The first dimension is the port.  The second is the impedance of 15, 20, 30 and 40 Ohms.  The 3rd dimension is the rate:3, 4,5 or 6 V/ns.  Computed and sent to the correct data blocks in phy_reset.  Also used in advanced training</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 4 4</array>
</attribute>

<attribute>
    <id>ATTR_ECID</id>
    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
    <description>Bits 0 to 63 of the ECID in array entry 0 and bits 64 to 127 in ECID array entry 1
Created from running the mss_get_cen_ecid.C
Firmware shares some code with the processor, so the attribute is named so they can point at a target and have common function.</description>
    <valueType>uint64</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_MSS_ALLOW_SINGLE_PORT</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>When this value is true, then mss_eff config will allow a single port to have one dimm and will allow ports to have different sizes.  Used in eff_config</description>
    <valueType>uint8</valueType>
    <enum>FALSE = 0, TRUE = 1</enum>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CLK_P0</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CLK_P1</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CLK_P0</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CLK_P1</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A0</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A1</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A2</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A3</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A4</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A5</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A6</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A7</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A8</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A9</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A10</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A11</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A12</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A13</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A14</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A15</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_BA0</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_BA1</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_BA2</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_CASN</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_RASN</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_WEN</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_PAR</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_PAR</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M_ACTN</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_ACTN</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CNTL_CKE0</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CNTL_CKE1</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CNTL_CKE2</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CNTL_CKE3</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CNTL_CSN0</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CNTL_CSN1</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CNTL_CSN2</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CNTL_CSN3</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CNTL_ODT0</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CNTL_ODT1</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CNTL_CKE0</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CNTL_CKE1</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CNTL_CKE2</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CNTL_CKE3</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CNTL_CSN0</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CNTL_CSN1</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CNTL_CSN2</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CNTL_CSN3</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CNTL_ODT0</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CNTL_ODT1</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_MSS_DQS_SWIZZLE_TYPE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>DQS Swizzle type is set by the platform to describe what kind of DQS connection is being used for register acceses. Type 0 is normal, type 1 is for systems with wiring like glacier 1.  Additional types maybe defined if new boards have even different DQS swizzle features</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_MSS_ZSERIES</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>Determines if the code is Zseries type or P Series.  The platform determines this and this attribute is mostly used in the initfiles so that we can share the same initialization code with the zSeries team</description>
    <valueType>uint8</valueType>
    <enum>FALSE = 0, TRUE = 1</enum>
    <platInit/>
    <odmVisable/>
</attribute>

<attribute>
    <id>ATTR_MSS_PSRO</id>
    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
    <description>Set by the centaur mss_get_cen_ecid function used diagnostic and chip characterization reporting</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
</attribute>

<attribute>
    <id>ATTR_MSS_NWELL_MISPLACEMENT</id>
    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
    <description>Set by the platform depending on DD1 vs DD1.01.  If true, then SI settings affected by the NWELL problem are adjusted.  Used in eff_config</description>
    <valueType>uint8</valueType>
    <enum>FALSE = 0, TRUE = 1</enum>
    <writeable/>
    <odmVisable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_2N_MODE_ENABLED</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Describes if this MBA is in 2N address mode.  The DIMM attributes associated with this MBA describes if this mode is needed for SI.  The MR Keyword of the VPD gives and indication of the value needed. Set by eff_config and consumed in the mba_def.initfile.</description>
    <valueType>uint8</valueType>
    <enum>FALSE = 0, TRUE = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_MSS_DIMM_POWER_TEST_REV</id>
    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
    <description>The power test revision number that is saved when data is saved on an ISDIMM.  If the power test changes, then a difference indicates that the power test needs to be rerun.  This attribute needs to stick around between IPLs</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <persistent/>
</attribute>

<attribute>
    <id>ATTR_CDIMM_SENSOR_MAP_PRIMARY</id>
    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
    <description>Custom DIMM Sensor Map for Primary I2C Port (1 byte of data):
0x00 No sensors attached
0x01 DIMM sensor 0 attached
0x02 DIMM sensor 1 attached
0x04 DIMM sensor 2 attached
0x08 DIMM sensor 3 attached
0x10 DIMM sensor 4 attached
0x20 DIMM sensor 5 attached
0x40 DIMM sensor 6 attached
0x80 DIMM sensor 7 attached
Comes from the VPD MW Keyword</description>
    <valueType>uint8</valueType>
    <platInit/>
    <odmVisable/>
</attribute>

<attribute>
    <id>ATTR_CDIMM_SENSOR_MAP_SECONDARY</id>
    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
    <description>Custom DIMM Sensor Map for Secondary I2C Port (1 byte of data):
0x00 No sensors attached
0x01 DIMM sensor 0 attached
0x02 DIMM sensor 1 attached
0x04 DIMM sensor 2 attached
0x08 DIMM sensor 3 attached
0x10 DIMM sensor 4 attached
0x20 DIMM sensor 5 attached
0x40 DIMM sensor 6 attached
0x80 DIMM sensor 7 attached
Comes from the VPD MW Keyword</description>
    <valueType>uint8</valueType>
    <platInit/>
    <odmVisable/>
</attribute>

<attribute>
    <id>ATTR_CDIMM_VPD_MASTER_POWER_SLOPE</id>
    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
    <description>Master Power Slope that comes from the VPD MW Keyword</description>
    <valueType>uint32</valueType>
    <platInit/>
    <odmVisable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_CDIMM_VPD_MASTER_POWER_INTERCEPT</id>
    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
    <description>Master Power Intercept that comes from the VPD MW Keyword</description>
    <valueType>uint32</valueType>
    <platInit/>
    <odmVisable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_CDIMM_VPD_SUPPLIER_POWER_SLOPE</id>
    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
    <description>Supplier Power Slope that comes from the VPD the MV Keyword</description>
    <valueType>uint32</valueType>
    <platInit/>
    <odmVisable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_CDIMM_VPD_SUPPLIER_POWER_INTERCEPT</id>
    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
    <description>Supplier Power Intercept that comes from MV Keyword</description>
    <valueType>uint32</valueType>
    <platInit/>
    <odmVisable/>
    <persistRuntime/>
</attribute>

<attribute>
    <id>ATTR_EFF_DRAM_ADDRESS_MIRRORING</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Address mirroring on the DIMM by rank, up to 4 ranks.  The bits meanings is 0x08 is rank 0 is mirrored, 0x04 rank 1 is mirrored, 0x02 rank 2 and 0x01 rank 3 is mirrored.  Comes from EFF config reading the VPD_DRAM_ADDRESS_MIRRORING from the AM keyword of the VPD.</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
</attribute>

<attribute>
    <id>ATTR_MSS_BLUEWATERFALL_BROKEN</id>
    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
    <description>Set by the platform depending on DD1.0X vs DD1.03 or newer.  If true, then draminit_train will modify dqs_clk_ps and gate to work around the issue. Set in get ecid which determines if we are at 1.03</description>
    <valueType>uint8</valueType>
    <enum>FALSE = 0, TRUE = 1</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_MCBIST_PATTERN</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Enables mcbist data pattern selection.</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_MCBIST_TEST_TYPE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Enables mcbist test type selection.</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_MCBIST_PRINTING_DISABLE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>MCBIST support for printing</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_MCBIST_DATA_ENABLE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>MCBIST support for enabling data</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_MCBIST_USER_RANK</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>MCBIST support for rank selection</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_MCBIST_USER_BANK</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>MCBIST support for bank selection</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_SCHMOO_MULTIPLE_SETUP_CALL</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>MCBIST for multiple setup</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_RLO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>This value comes from looking at the ATTR_VPD_RLO attribute associated with the DIMMs off the port.  Computed in eff_config. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_CKE_PRI_MAP</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Contains the CKE MAP for the DIMM being plugged in.  The source of the data comes from the the ATTR_CKE_PRI_MAP attributes where 16 bits associated with port A data and 16 bits with B. This value goes directly into the MBA01 Rank-to-primary-CKE mapping table register bits 0:31 (MBA01_MBAREF1Q) register. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description>
    <valueType>uint32</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_CKE_PWR_MAP</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Contains the CKE Power Domain mapping tables for the DIMM being plugged in.  The source of the data are the ATTR_VPD_CKE_PWR_MAP with 32 bits coming from the attribute  associated  with port A data and 32 bits with B. This value goes directly into the MBA01 Rank-to-CKE power domain mapping table bits 0:33 (MBA01_MBARPC1Q) register. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description>
    <valueType>uint64</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_GPO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Global Phy Offset value that is used in setting up the phy.  This value is dervived from the VPD_GPO attribute. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_RDTAG</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Read Tag value that is used in setting up the phy.  It is expected that this value will come from the VPD. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_WLO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>This value comes from looking at the ATTR_VPD_WLO attribute associated with the DIMMs off the port.  Computed in eff_config. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_TSYS_ADR</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>TSYS for all address blocks in the MBA pair. This value comes from ATTR_VPD_TSYS_ADR of the assoicated DIMMs. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_TSYS_DP18</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>TSYS for all DP18 blocks in the MBA pair.  This value comes from ATTR_VPD_TSYS_DP18 from the associated DIMMs. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_EFF_DQ_WR_OFFSET</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>DQ write offset value that is used in setting up the phy's phase rotators before WR_LVL, 0x40 is HW Default.  It is expected that this value will come from the VPD</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2</array>
</attribute>

<attribute>
    <id>ATTR_EFF_BUFFER_LATENCY</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Additional buffer latency in the case of RDIMMs and LRDIMMs.    It is expected that this value will come from the VPD</description>
    <valueType>uint8</valueType>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_LRDIMM_MR12_REG</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>LRDIMM MR1,2 register.
DRAM Rtt_WR for all ranks, DRAM Rtt_Nom for ranks 0 and 1, DRAM driver impedance for all ranks.  Eff config should set this up.</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
</attribute>

<attribute>
    <id>ATTR_LRDIMM_ADDITIONAL_CNTL_WORDS</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>LRDIMM additional RCD control words as set by DIMM SPD:
F[3,4]RC10, F[3,4]RC11, F[5,6]RC10, F[5,6]RC11, F[7,8]RC10, F[7,8]RC11, F[9,10]RC10, F[9,10]RC11,
F[1]RC8, F[3]RC9, F[3]RC8, F[1]RC11, F[1]RC12, F[1]RC13, F[1]RC14, F[1]RC15.
Eff config should set this up</description>
    <valueType>uint64</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <array> 2 2</array>
</attribute>

<attribute>
    <id>ATTR_LRDIMM_RANK_MULT_MODE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>LRDIMM rank multiplication mode.
Will be set at an MBA level with one policy to be used</description>
    <valueType>uint8</valueType>
    <enum>NORMAL = 0, 2X_MULT = 2, 4X_MULT = 4</enum>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_L4_BANK_DELETE_VPD</id>
    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
    <description>L4 Bank Delete settings in VPD.
Denotes what banks have been deleted from the L4.
Data will be pulled from CDIMM VPD if CDIMM present.
Data will be pulled from backplane VPD if IS DIMMs present.</description>
    <valueType>uint32</valueType>
    <writeable/>
    <persistent/>
</attribute>

<attribute>
    <id>ATTR_MSS_DIMM_POWER_TEST_MEM_THROTTLE_NUMERATOR_PER_MBA</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>runtime memory throttle values adjusted by the dimm power test
DIMM power test memory throttles for cfg_nm_n_per_mba</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <persistent/>
</attribute>

<attribute>
    <id>ATTR_MSS_DIMM_POWER_TEST_MEM_THROTTLE_NUMERATOR_PER_CHIP</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>runtime memory throttle values adjusted by the dimm power test
DIMM power test memory throttles for cfg_nm_n_per_chip</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <persistent/>
</attribute>

<attribute>
    <id>ATTR_MSS_DIMM_POWER_TEST_MEM_THROTTLE_DENOMINATOR</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>runtime memory throttle values adjusted by the dimm power test
DIMM power test memory throttles for cfg_nm_m</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
    <persistent/>
</attribute>

<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP
<attribute>
    <id>ATTR_MSS_DRAM_ACTIVATE_POWER_PERCENT</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>DRAM Activation power percentage to determine the ras and cas weights for throttle controls
will originates from VPD for custom DIMMs in the MW keyword byte 5 (MSB is on the left(big endian))
</description>
    <valueType>uint8</valueType>
    <platInit/>
    <odmVisable/>
</attribute>
-->

<attribute>
    <id>ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>RAS weight to use for memory throttle control - set in thermal procedures</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>CAS weight to use for memory throttle control - set in thermal procedures</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP
<attribute>
    <id>ATTR_VPD_CKE_PRI_MAP</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>This value comes from the VPD keyword MT bytes 54 and 55 MT(54:55) for the Logical DIMM associated with port A.  Bytes 118:119 for port B, 182:183 for port C and 246:247 for port D.  In the end, the AB and CD portions form a 32 bit word for each mba to write into the corresponding ddrphy register</description>
    <valueType>uint32</valueType>
    <platInit/>
    <odmVisable/>
    <array>2</array>
</attribute>

<attribute>
    <id>ATTR_VPD_CKE_PWR_MAP</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>This value comes from the VPD keyword MT bytes 56 to 59 MT(56:59) for the Logical DIMM associated with port A.  Bytes 120:123 for port B, 184:187 for port C and 248:251 for port D</description>
    <valueType>uint32</valueType>
    <platInit/>
    <odmVisable/>
    <array>2</array>
</attribute>

<attribute>
    <id>ATTR_VPD_GPO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>This value comes from the VPD keyword MT bytes 61 MT(61) for the Logical DIMM associated with port A.  Bytes 125 for port B, 189 for port C and 253 for port D</description>
    <valueType>uint8</valueType>
    <platInit/>
    <odmVisable/>
    <array>2</array>
</attribute>

<attribute>
    <id>ATTR_VPD_RLO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>This value comes from the VPD keyword MT byte 60 bits 4:7 for the Logical DIMM associated with port A.  Byte 124 bits 4:7 for port B, 188 bits 4:7 for port C and 252 bits 4:7 for port D</description>
    <valueType>uint8</valueType>
    <platInit/>
    <odmVisable/>
    <array>2</array>
</attribute>

<attribute>
    <id>ATTR_VPD_WLO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>This value comes from the VPD keyword MT byte 60 bits 0:3 for the Logical DIMM associated with port A.  Byte 124 bits 0:3 for port B, 188 bits 0:3 for port C and 252 bits 0:3 for port D</description>
    <valueType>uint8</valueType>
    <platInit/>
    <odmVisable/>
    <array>2</array>
</attribute>

<attribute>
    <id>ATTR_VPD_TSYS_ADR</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>This value comes from the VPD MR keyword byte 49 for ports A and B and byte 177 for port C and D.    This means that all ADR blocks use this value on an mba level</description>
    <valueType>uint8</valueType>
    <platInit/>
    <odmVisable/>
    <array>2</array>
</attribute>

<attribute>
    <id>ATTR_VPD_TSYS_DP18</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>This value comes from the VPD MR keyword byte 113 for ports A and B and byte 241 for port C and D.  This means all DP18 blocks use this value on a mba level</description>
    <valueType>uint8</valueType>
    <platInit/>
    <odmVisable/>
    <array>2</array>
</attribute>

<attribute>
    <id>ATTR_VPD_MT_CKE_PRI_MAP</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>OBSOLETE - See ATTR_VPD_CKE_PRI_MAP</description>
    <valueType>uint32</valueType>
    <platInit/>
    <odmVisable/>
    <array>2</array>
</attribute>

<attribute>
    <id>ATTR_VPD_MT_CKE_PWR_MAP</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>OBSOLETE - See ATTR_VPD_CKE_PWR_MAP</description>
    <valueType>uint32</valueType>
    <platInit/>
    <odmVisable/>
    <array>2</array>
</attribute>

<attribute>
    <id>ATTR_VPD_MR_GPO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>OBSOLETE - see ATTR_VPD_GPO</description>
    <valueType>uint8</valueType>
    <platInit/>
    <odmVisable/>
    <array>2</array>
</attribute>

<attribute>
    <id>ATTR_VPD_MR_RLO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>OBSOLETE - see ATTR_VPD_RLO</description>
    <valueType>uint8</valueType>
    <platInit/>
    <odmVisable/>
    <array>2</array>
</attribute>

<attribute>
    <id>ATTR_VPD_MR_WLO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>OBSOLETE - see ATTR_VPD_WLO</description>
    <valueType>uint8</valueType>
    <platInit/>
    <odmVisable/>
    <array>2</array>
</attribute>

<attribute>
    <id>ATTR_VPD_MR_TSYS_ADR</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>OBSOLETE see ATTR_VPD_TSYS_ADR</description>
    <valueType>uint8</valueType>
    <platInit/>
    <odmVisable/>
    <array>2</array>
</attribute>

<attribute>
    <id>ATTR_VPD_MR_TSYS_DP18</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>OBSOLETE see ATTR_VPD_TSYS_DP18</description>
    <valueType>uint8</valueType>
    <platInit/>
    <odmVisable/>
    <array>2</array>
</attribute>
-->

<attribute>
    <id>ATTR_VPD_CKE_PRI_MAP</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>This value comes from the VPD keyword MT bytes 54 and 55 MT(54:55) for the Logical DIMM associated with port A.  Bytes 118:119 for port B, 182:183 for port C and 246:247 for port D.  In the end, the AB and CD portions form a 32 bit word for each mba to write into the corresponding ddrphy register</description>
    <valueType>uint32</valueType>
    <platInit/>
    <odmVisable/>
    <array>2</array>
</attribute>

<attribute>
    <id>ATTR_VPD_CKE_PWR_MAP</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>This value comes from the VPD keyword MT bytes 56 to 59 MT(56:59) for the Logical DIMM associated with port A.  Bytes 120:123 for port B, 184:187 for port C and 248:251 for port D</description>
    <valueType>uint32</valueType>
    <platInit/>
    <odmVisable/>
    <array>2</array>
</attribute>

<attribute>
    <id>ATTR_VPD_GPO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>This value comes from the VPD keyword MT bytes 61 MT(61) for the Logical DIMM associated with port A.  Bytes 125 for port B, 189 for port C and 253 for port D</description>
    <valueType>uint8</valueType>
    <platInit/>
    <odmVisable/>
    <array>2</array>
</attribute>

<attribute>
    <id>ATTR_VPD_RLO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>This value comes from the VPD keyword MT byte 60 bits 4:7 for the Logical DIMM associated with port A.  Byte 124 bits 4:7 for port B, 188 bits 4:7 for port C and 252 bits 4:7 for port D</description>
    <valueType>uint8</valueType>
    <platInit/>
    <odmVisable/>
    <array>2</array>
</attribute>

<attribute>
    <id>ATTR_VPD_WLO</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>This value comes from the VPD keyword MT byte 60 bits 0:3 for the Logical DIMM associated with port A.  Byte 124 bits 0:3 for port B, 188 bits 0:3 for port C and 252 bits 0:3 for port D</description>
    <valueType>uint8</valueType>
    <platInit/>
    <odmVisable/>
    <array>2</array>
</attribute>

<attribute>
    <id>ATTR_VPD_TSYS_ADR</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>This value comes from the VPD MR keyword byte 49 for ports A and B and byte 177 for port C and D.    This means that all ADR blocks use this value on an mba level</description>
    <valueType>uint8</valueType>
    <platInit/>
    <odmVisable/>
    <array>2</array>
</attribute>

<attribute>
    <id>ATTR_VPD_TSYS_DP18</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>This value comes from the VPD MR keyword byte 113 for ports A and B and byte 241 for port C and D.  This means all DP18 blocks use this value on a mba level</description>
    <valueType>uint8</valueType>
    <platInit/>
    <odmVisable/>
    <array>2</array>
</attribute>

<attribute>
    <id>ATTR_LAB_USE_JTAG_MODE</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>This attribute controls how the procedures operate in JTAG mode under an environment called cronus flex.  For normal operation, this attribute should be set to FALSE. Platforms should initialize this attribute to FALSE.</description>
    <valueType>uint8</valueType>
    <enum>FALSE =0, TRUE = 1</enum>
    <platInit/>
    <odmVisable/>
</attribute>

<attribute>
    <id>ATTR_MSS_CONTROL_SWITCH</id>
    <targetType>TARGET_TYPE_SYSTEM</targetType>
    <description>This attribute enables control switches in the memory code.  This is a one hot vector:  Bit 7 controls the Bad Bit Mask function in draminit_training. The platform should initialize this to BBM_ON except if ATTR_LAB_USE_JTAG_MODE == TRUE, then the platform should set this attribute to BBM_ OFF.</description>
    <valueType>uint8</valueType>
    <enum>BBM_ON = 0x01, BBM_OFF = 0x00 </enum>
    <platInit/>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_MCBIST_RANDOM_SEED_VALUE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Controls the MCBIST engine in the centaur chip.  The value will be set in mss_eff_config_shmoo.</description>
    <valueType>uint32</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<attribute>
    <id>ATTR_MCBIST_RANDOM_SEED_TYPE</id>
    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
    <description>Controls the MCBIST engine in the centaur chip.  The value will be set in mss_eff_config_shmoo.</description>
    <valueType>uint8</valueType>
    <writeable/>
    <odmVisable/>
    <odmChangeable/>
</attribute>

<!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB -->
<!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP -->
</attributes>