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#-- $Id: p8.pe.phase2.scom.initfile,v 1.5 2013/11/13 17:20:20 jmcgill Exp $
#-------------------------------------------------------------------------------
#--
#-- (C) Copyright International Business Machines Corp. 2011
#-- All Rights Reserved -- Property of IBM
#-- *** IBM Confidential ***
#--
#-- TITLE : p8.pcie.phase2.scom.initfile
#-- DESCRIPTION : Perform PCIe PBCQ/AIB Inits (Phase 2, Steps 9-17)
#--
#-- OWNER NAME : Joe McDonald Email: joemc@us.ibm.com
#-- OWNER NAME : Rick Mata Email: ricmata@us.ibm.com
#--
#--------------------------------------------------------------------------------
SyntaxVersion = 1
#--------------------------------------------------------------------------------
#-- Includes
#--------------------------------------------------------------------------------
#--------------------------------------------------------------------------------
#-- Defines
#--------------------------------------------------------------------------------
define def_nest_freq_r0 = (SYS.ATTR_FREQ_PB >= 2200);
define def_nest_freq_r1 = ((SYS.ATTR_FREQ_PB <= 1700) && (SYS.ATTR_FREQ_PB < 2200));
define def_nest_freq_r2 = (SYS.ATTR_FREQ_PB < 1700);
define enable_enh_ive_ordering = (ATTR_CHIP_EC_FEATURE_ENABLE_IVE_PERFORMANCE_ORDERING != 0);
define enable_dmar_ooo = (ATTR_CHIP_EC_FEATURE_ENABLE_PCI_DMAR_OOO != 0);
#--------------------------------------------------------------------------------
#-- SCOM initializations
#--------------------------------------------------------------------------------
#-- PBCQ Mode Control Register
scom 0x02012(0,4,8)0B {
bits, scom_data, expr;
12, 0b1, any; #-- disable group scope on TCE read requests
26, 0b1, (enable_enh_ive_ordering); #-- enable enhanced IVE performance ordering only where supported (HW226407)
27, 0b1, any; #-- force IVE write operations to system scope
}
#-- PCI Hardware Configuration 0 Register
scom 0x02012(0,4,8)18 {
bits, scom_data;
0:3, 0b0000; #-- hang poll scale (reg=0, scale of 1)
4:7, 0b0010; #-- data poll scale (reg=2, scale of 3)
8:11, 0b0000; #-- data poll scale (PE) (reg=0, scale of 1)
17, 0b1; #-- disable out-of-order store behavior
}
#-- PCI Hardware Configuration 1 Register
scom 0x02012(0,4,8)19 {
bits, scom_data;
22, 0b0; #-- diable OOO DMA read
}
#-- PCI Nest Clock Trace Control Register
scom 0x02012(0,4,8)0D {
bits, scom_data;
0:3, 0b1001; #-- enable trace, select inbound + address info
}
#-- PB AIB Control/Status Register
scom 0x09012(0,4,8)0F {
bits, scom_data, expr;
0:2, 0b011, (def_nest_freq_r0); #-- Maximum Ch0 command credit given to ETU
0:2, 0b010, (def_nest_freq_r1);
0:2, 0b001, (def_nest_freq_r2);
3:5, 0b001, any; #-- Maximum Ch1 command credit given to ETU
6:8, 0b011, (def_nest_freq_r0); #-- Maximum Ch2 command credit given to ETU
6:8, 0b010, (def_nest_freq_r1 || def_nest_freq_r2);
9:11, 0b000, any; #-- Maximum Ch3 command credit given to ETU
12:13, 0b11, any; #-- Overcommit of inbound speed matching buffer (HW245629)
30:31, 0b11, any; #-- enable PCI clock tracing w/ ETU as default
}
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