1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
|
#-- $Id: p8.pe.phase2.scom.initfile,v 1.7 2015/02/16 22:21:07 ricmata Exp $
#-------------------------------------------------------------------------------
#--
#-- (C) Copyright International Business Machines Corp. 2011
#-- All Rights Reserved -- Property of IBM
#-- *** ***
#--
#-- TITLE : p8.pcie.phase2.scom.initfile
#-- DESCRIPTION : Perform PCIe PBCQ/AIB Inits (Phase 2, Steps 9-17)
#--
#-- OWNER NAME : Joe McDonald Email: joemc@us.ibm.com
#-- OWNER NAME : Rick Mata Email: ricmata@us.ibm.com
#--
#--------------------------------------------------------------------------------
SyntaxVersion = 1
#--------------------------------------------------------------------------------
#-- Includes
#--------------------------------------------------------------------------------
#--------------------------------------------------------------------------------
#-- Defines
#--------------------------------------------------------------------------------
define phb0 = (ATTR_PROC_PCIE_NUM_PHB >= 1);
define phb1 = (ATTR_PROC_PCIE_NUM_PHB >= 2);
define phb2 = (ATTR_PROC_PCIE_NUM_PHB >= 3);
define phb3 = (ATTR_PROC_PCIE_NUM_PHB >= 4);
define def_nest_freq_r0 = (SYS.ATTR_FREQ_PB >= 2200);
define def_nest_freq_r1 = ((SYS.ATTR_FREQ_PB <= 1700) && (SYS.ATTR_FREQ_PB < 2200));
define def_nest_freq_r2 = (SYS.ATTR_FREQ_PB < 1700);
define enable_enh_ive_ordering = (ATTR_CHIP_EC_FEATURE_ENABLE_IVE_PERFORMANCE_ORDERING != 0);
define enable_dmar_ooo = (ATTR_CHIP_EC_FEATURE_ENABLE_PCI_DMAR_OOO != 0);
#--------------------------------------------------------------------------------
#-- SCOM initializations
#--------------------------------------------------------------------------------
#-- PBCQ Mode Control Register
scom 0x0201200B {
bits, scom_data, expr;
12, 0b1, (phb0); #-- disable group scope on TCE read requests
26, 0b1, (phb0 && enable_enh_ive_ordering); #-- enable enhanced IVE performance ordering only where supported (HW226407)
27, 0b1, (phb0); #-- force IVE write operations to system scope
}
scom 0x0201240B {
bits, scom_data, expr;
12, 0b1, (phb1);
26, 0b1, (phb1 && enable_enh_ive_ordering);
27, 0b1, (phb1);
}
scom 0x0201280B {
bits, scom_data, expr;
12, 0b1, (phb2);
26, 0b1, (phb2 && enable_enh_ive_ordering);
27, 0b1, (phb2);
}
scom 0x02012C0B {
bits, scom_data, expr;
12, 0b1, (phb3);
26, 0b1, (phb3 && enable_enh_ive_ordering);
27, 0b1, (phb3);
}
#-- PCI Hardware Configuration 0 Register
scom 0x02012018 {
bits, scom_data, expr;
0:3, 0b0001, (phb0); #-- hang poll scale (reg=1, value of 6)
4:7, 0b0010, (phb0); #-- data poll scale (reg=2, value of 9)
8:11, 0b0001, (phb0); #-- data poll scale (PE) (reg=1, value of 6)
17, 0b1, (phb0); #-- disable out-of-order store behavior
}
scom 0x02012418 {
bits, scom_data, expr;
0:3, 0b0001, (phb1);
4:7, 0b0010, (phb1);
8:11, 0b0001, (phb1);
17, 0b1, (phb1);
}
scom 0x02012818 {
bits, scom_data, expr;
0:3, 0b0001, (phb2);
4:7, 0b0010, (phb2);
8:11, 0b0001, (phb2);
17, 0b1, (phb2);
}
scom 0x02012C18 {
bits, scom_data, expr;
0:3, 0b0001, (phb3);
4:7, 0b0010, (phb3);
8:11, 0b0001, (phb3);
17, 0b1, (phb3);
}
#-- PCI Hardware Configuration 1 Register
scom 0x02012019 {
bits, scom_data, expr;
22, 0b0, (phb0); #-- diable OOO DMA read
}
scom 0x02012419 {
bits, scom_data, expr;
22, 0b0, (phb1);
}
scom 0x02012819 {
bits, scom_data, expr;
22, 0b0, (phb2);
}
scom 0x02012C19 {
bits, scom_data, expr;
22, 0b0, (phb3);
}
#-- PCI Nest Clock Trace Control Register
scom 0x0201200D {
bits, scom_data, expr;
0:3, 0b1001, (phb0); #-- enable trace, select inbound + address info
}
scom 0x0201240D {
bits, scom_data, expr;
0:3, 0b1001, (phb1);
}
scom 0x0201280D {
bits, scom_data, expr;
0:3, 0b1001, (phb2);
}
scom 0x02012C0D {
bits, scom_data, expr;
0:3, 0b1001, (phb3);
}
#-- PB AIB Control/Status Register
scom 0x0901200F {
bits, scom_data, expr;
0:2, 0b011, (phb0 && def_nest_freq_r0); #-- Maximum Ch0 command credit given to ETU
0:2, 0b010, (phb0 && def_nest_freq_r1);
0:2, 0b001, (phb0 && def_nest_freq_r2);
3:5, 0b001, (phb0); #-- Maximum Ch1 command credit given to ETU
6:8, 0b011, (phb0 && def_nest_freq_r0); #-- Maximum Ch2 command credit given to ETU
6:8, 0b010, (phb0 && (def_nest_freq_r1 || def_nest_freq_r2));
9:11, 0b000, (phb0); #-- Maximum Ch3 command credit given to ETU
12:13, 0b11, (phb0); #-- Overcommit of inbound speed matching buffer (HW245629)
30:31, 0b11, (phb0); #-- enable PCI clock tracing w/ ETU as default
}
scom 0x0901240F {
bits, scom_data, expr;
0:2, 0b011, (phb1 && def_nest_freq_r0);
0:2, 0b010, (phb1 && def_nest_freq_r1);
0:2, 0b001, (phb1 && def_nest_freq_r2);
3:5, 0b001, (phb1);
6:8, 0b011, (phb1 && def_nest_freq_r0);
6:8, 0b010, (phb1 && (def_nest_freq_r1 || def_nest_freq_r2));
9:11, 0b000, (phb1);
12:13, 0b11, (phb1);
30:31, 0b11, (phb1);
}
scom 0x0901280F {
bits, scom_data, expr;
0:2, 0b011, (phb2 && def_nest_freq_r0);
0:2, 0b010, (phb2 && def_nest_freq_r1);
0:2, 0b001, (phb2 && def_nest_freq_r2);
3:5, 0b001, (phb2);
6:8, 0b011, (phb2 && def_nest_freq_r0);
6:8, 0b010, (phb2 && (def_nest_freq_r1 || def_nest_freq_r2));
9:11, 0b000, (phb2);
12:13, 0b11, (phb2);
30:31, 0b11, (phb2);
}
scom 0x09012C0F {
bits, scom_data, expr;
0:2, 0b011, (phb3 && def_nest_freq_r0);
0:2, 0b010, (phb3 && def_nest_freq_r1);
0:2, 0b001, (phb3 && def_nest_freq_r2);
3:5, 0b001, (phb3);
6:8, 0b011, (phb3 && def_nest_freq_r0);
6:8, 0b010, (phb3 && (def_nest_freq_r1 || def_nest_freq_r2));
9:11, 0b000, (phb3);
12:13, 0b11, (phb3);
30:31, 0b11, (phb3);
}
|
