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|
#-- $Id: p8.abus.custom.scom.initfile,v 1.18 2015/04/13 16:17:02 jgrell Exp $
#-- CHANGE HISTORY:
#--------------------------------------------------------------------------------
#-- Version:|Author: | Date: | Comment:
#-- --------|--------|--------|--------------------------------------------------
#-- 1.18|jgrell |04/25/15| Updated attribute to system type at Thi's request so it can be applied to Brazos only. (SW299500)
#-- 1.17|jmcgill |03/24/15| remove l2u delay settings,given filter bypass soln (SW299659)
#-- 1.15|jgrell |02/25/15| Added rx_fifo_final_l2u_dly for Venice only (SW296793)
#-- 1.14|garyp |02/19/14| Added rx_min_eye_width and rx_min_eye_height for manufacturing and lab thresholding
#-- 1.13|jgrell |02/12/14| Added rx_wt_lane_disabled=1 on lane 17 (SW244284)
#-- 1.12|jgrell |12/03/13| Set rx_eo_ddc_timeout_sel to 110 for DD2
#-- 1.11|jgrell |10/29/13| Changed rx_ds_timeout_sel setting to 111
#-- 1.9 |jgrell |10/28/13| Re-enabled recal bits for DD2+ hw
#-- 1.8 |jgrell |09/24/13| Changed "1" expression to "any"
#-- 1.6 |jgrell |09/17/13| Added DD2 specific inits
#-- 1.4 |jgrell |06/18/13| Added Venice specific PRBS tap IDs due to common initfile
#-- 1.3 |thomsen |04/30/13| Added TGT1. to ATTR_CHIP_EC* attribute instances to reference a chip target rather than a chiplet target
#-- 1.2 |jgrell |04/18/13| Added EC controled Recal enables
#-- 1.1 |thomsen |01/29/13| Created initial version
#-- --------|--------|--------|--------------------------------------------------
#--------------------------------------------------------------------------------
# End of revision history
#--------------------------------------------------------------------------------
#--Master list of variables that can be used in this file is at:
#--<Attribute Definition Location>
SyntaxVersion = 1
#--******************************************************************************
#-- -----------------------------------------------------------------------------
#--
#-- Includes
#-- Note: Must include the path to the .define file.
#--
#-- -----------------------------------------------------------------------------
#--******************************************************************************
include edi.io.define
#--******************************************************************************
#-- -----------------------------------------------------------------------------
#--
#-- Defines
#--
#-- -----------------------------------------------------------------------------
#--******************************************************************************
define def_all_lanes=11111;
#--*****************
#-- set rx_min_eye_width and rx_min_eye_height if in manufacturing mode
#--*****************
scom 0x800.0b(rx_result_chk_pg)(rx_grp0)(lane_na).0x(abus_gcr_addr) {
bits, scom_data, expr;
rx_min_eye_width, SYS.ATTR_MNFG_ABUS_MIN_EYE_WIDTH, ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0);
rx_min_eye_height, SYS.ATTR_MNFG_ABUS_MIN_EYE_HEIGHT, ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0);
}
#--******************************************************************************
#--------------------------------------------------------------------------------
# __ ____ __ __
# / / ____ _____ ___ / __ \____ _ _____ _____ / / / /___
# / / / __ `/ __ \/ _ \ / /_/ / __ \ | /| / / _ \/ ___/ / / / / __ \
# / /___/ /_/ / / / / __/ / ____/ /_/ / |/ |/ / __/ / / /_/ / /_/ /
# /_____/\__,_/_/ /_/\___/ /_/ \____/|__/|__/\___/_/ \____/ .___/
# /_/
#--------------------------------------------------------------------------------
#--******************************************************************************
### # rx_lane_pdwn
### scom 0x800.0b(rx_mode_pl)(tx_grp0)(def_all_lanes).0x(abus_gcr_addr) {
### bits, scom_data;
### rx_lane_pdwn, 0b0;
### }
### # tx_lane_pdwn
### scom 0x800.0b(tx_mode_pl)(tx_grp0)(def_all_lanes).0x(abus_gcr_addr) {
### bits, scom_data;
### tx_lane_pdwn, 0b0;
### }
#--******************************************************************************
#--------------------------------------------------------------------------------
# _______ __ __ ___ _ ________ _____ ___ ____________ ______
# /_ __/ |/ / / / / | / | / / ____/ / _/ | / / | / / ____/ __ \/_ __/
# / / | / / / / /| | / |/ / __/ / // |/ /| | / / __/ / /_/ / / /
# / / / | / /___/ ___ |/ /| / /___ _/ // /| / | |/ / /___/ _, _/ / /
# /_/ /_/|_| /_____/_/ |_/_/ |_/_____/ /___/_/ |_/ |___/_____/_/ |_| /_/
# figlet -fslant
#--------------------------------------------------------------------------------
#--******************************************************************************
# These only do a scom if the invert attribute is set (saves scom's).
# The default scanflush value of tx_lane_invert for each lane is '0'.
# Lane 0
# 0x8004040008010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_0).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x80000000) > 0);
}
#
# Lane 1
# 0x8004040108010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_1).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x40000000) > 0);
}
#
# Lane 2
# 0x8004040208010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_2).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x20000000) > 0);
}
#
# Lane 3
# 0x8004040308010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_3).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x10000000) > 0);
}
#
# Lane 4
# 0x8004040408010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_4).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x08000000) > 0);
}
#
# Lane 5
# 0x8004040508010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_5).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x04000000) > 0);
}
#
# Lane 6
# 0x8004040608010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_6).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x02000000) > 0);
}
#
# Lane 7
# 0x8004040708010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_7).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x01000000) > 0);
}
#
# Lane 8
# 0x8004040808010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_8).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00800000) > 0);
}
#
# Lane 9
# 0x8004040908010C3F{
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_9).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00400000) > 0);
}
#
# Lane 10
# 0x8004040A08010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_10).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00200000) > 0);
}
# Lane 11
# 0x8004040B08010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_11).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00100000) > 0);
}
#
# Lane 12
# 0x8004040C08010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_12).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00080000) > 0);
}
#
# Lane 13
# 0x8004040D08010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_13).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00040000) > 0);
}
#
# Lane 14
# 0x8004040E08010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_14).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00020000) > 0);
}
#
# Lane 15
# 0x8004040F08010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_15).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00010000) > 0);
}
#
# Lane 16
# 0x8004041008010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_16).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00008000) > 0);
}
# Lane 17
# 0x8004042008010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_17).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00004000) > 0);
}
# Lane 18
# 0x8004043008010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_18).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00002000) > 0);
}
# Lane 19
# 0x8004044008010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_19).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00001000) > 0);
}
# Lane 20
# 0x8004045008010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_20).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00000800) > 0);
}
# Lane 21
# 0x8004046008010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_21).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00000400) > 0);
}
# Lane 22
# 0x8004047008010C3F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_22).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00000200) > 0);
}
#--******************************************************************************
#--------------------------------------------------------------------------------
# _____ _ _ _______ _ _ ___ _
# /_ __/ |/ / / ____/ / / //_/ / _/___ _ _____ _____/ /
# / / | / / / / / / ,< / // __ \ | / / _ \/ ___/ __/
# / / / | / /___/ /___/ /| | _/ // / / / |/ / __/ / / /
# /_/ /_/|_| \____/_____/_/ |_| /___/_/ /_/|___/\___/_/ \__/
# figlet -fslant
#--------------------------------------------------------------------------------
#--******************************************************************************
# CLK Lane (assigned to bit 31 of TX Lane Invert Attribute)
# 0x800???7008010C3F
scom 0x800.0b(tx_clk_mode_pg)(tx_grp0)(lane_na).0x(abus_gcr_addr) {
bits, scom_data, expr;
tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00000001) > 0);
}
#--******************************************************************************
#--------------------------------------------------------------------------------
# __ ________ ____ _____
# / |/ / ___// __ ) / ___/ ______ _____
# / /|_/ /\__ \/ __ | \__ \ | /| / / __ `/ __ \
# / / / /___/ / /_/ / ___/ / |/ |/ / /_/ / /_/ /
# /_/ /_//____/_____/ /____/|__/|__/\__,_/ .___/
# /_/
# figlet -fslant
#--------------------------------------------------------------------------------
#--******************************************************************************
# 0x800C1C0008010C3F
scom 0x800.0b(tx_mode_pg)(tx_grp0)(lane_na).0x(abus_gcr_addr) {
bits, scom_data;
tx_msbswap, (ATTR_EI_BUS_TX_MSBSWAP & 0x01);
}
#--**************************************************************************************************************
#----------------------------------------------------------------------------------------------------------------
# Recal
#----------------------------------------------------------------------------------------------------------------
#--**************************************************************************************************************
# HW235842
scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp0)(lane_na).0x(abus_gcr_addr) {
bits, scom_data, expr;
rx_rc_enable_dfe_h1_cal, 0b0, TGT1.ATTR_CHIP_EC_FEATURE_RECAL_DFE_ENABLE==0;
rx_rc_enable_ddc, 0b0, TGT1.ATTR_CHIP_EC_FEATURE_RECAL_DDC_ENABLE==0;
rx_rc_enable_ctle_cal, 0b0, TGT1.ATTR_CHIP_EC_FEATURE_RECAL_CTLE_ENABLE==0;
}
#--**************************************************************************************************************
#----------------------------------------------------------------------------------------------------------------
# Power Down Unused Lanes
#----------------------------------------------------------------------------------------------------------------
#--**************************************************************************************************************
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_23).0x(abus_gcr_addr) {
bits, scom_data;
tx_lane_pdwn, 0b1;
}
scom 0x800.0b(rx_mode_pl)(rx_grp0)(lane_23).0x(abus_gcr_addr) {
bits, scom_data;
rx_lane_pdwn, 0b1;
}
scom 0x800.0b(rx_wt_status_pl)(rx_grp0)(lane_23).0x(abus_gcr_addr) {
bits, scom_data;
rx_wt_lane_disabled, 0b1;
}
#--**************************************************************************************************************
#----------------------------------------------------------------------------------------------------------------
# Venice Specific Inits
#----------------------------------------------------------------------------------------------------------------
#--**************************************************************************************************************
#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004341408010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b010, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004341508010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b001, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004341308010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b011, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004341608010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b000, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004341108010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b101, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004341008010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b110, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004341208010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b100, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004340F08010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b111, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#2.TXPACK_2.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004340C08010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b010, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#2.TXPACK_2.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004340D08010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b001, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#2.TXPACK_2.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004340E08010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b000, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004340108010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b001, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004340208010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b010, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004340008010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b000, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004340308010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b011, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004340608010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b110, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004340508010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b101, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004340708010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b111, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004340408010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b100, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#5.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004340908010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b001, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#5.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004340A08010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b010, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#5.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004340808010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b000, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#TX_WRAP.TX0.TXPACKS#5.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
scom 0x8004340B08010C3F {
bits, scom_data, expr;
tx_prbs_tap_id, 0b011, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
}
#--***********************************************************************************
#-------------------------------------------------------------------------------------
#-- Brazos only
#-------------------------------------------------------------------------------------
#--***********************************************************************************
scom 0x800.0b(rx_fifo_mode_pg)(rx_grp0)(lane_na).0x(abus_gcr_addr) {
bits, scom_data, expr;
rx_fifo_final_l2u_dly, 0b0011, SYS.ATTR_BRAZOS_RX_FIFO_OVERRIDE==1;
}
#--***********************************************************************************
#-------------------------------------------------------------------------------------
#-- DD2+ Murano & Venice
#-------------------------------------------------------------------------------------
#--***********************************************************************************
scom 0x800.0b(rx_timeout_sel_pg)(rx_grp0)(lane_na).0x(abus_gcr_addr) {
bits, scom_data, expr;
rx_sls_timeout_sel_dd2, 0b1010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0;
rx_ds_bl_timeout_sel_dd2, 0b101, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0;
rx_cl_timeout_sel_dd2, 0b010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0;
rx_wt_timeout_sel_dd2, 0b111, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0;
rx_ds_timeout_sel_dd2, 0b111, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0;
}
scom 0x800.0b(rx_timeout_sel1_pg)(rx_grp0)(lane_na).0x(abus_gcr_addr) {
bits, scom_data, expr;
rx_eo_ddc_timeout_sel, 0b110, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0;
}
############################################################################################
# END OF FILE
############################################################################################
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