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path: root/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_TP.rule
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# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_TP.rule $
#
# IBM CONFIDENTIAL
#
# COPYRIGHT International Business Machines Corp. 2012,2013
#
# p1
#
# Object Code Only (OCO) source materials
# Licensed Internal Code Source Materials
# IBM HostBoot Licensed Internal Code
#
# The source code for this program is not published or otherwise
# divested of its trade secrets, irrespective of what has been
# deposited with the U.S. Copyright Office.
#
# Origin: 30
#
# IBM_PROLOG_END_TAG

    ############################################################################
    # TP Chiplet Registers
    ############################################################################

    register TP_CHIPLET_CS_FIR
    {
        name        "TPTOP.TPC.XFIR";
        scomaddr    0x01040000;
        capture     group default;
        capture     group FirRegs;
    };

    register TP_CHIPLET_RE_FIR
    {
        name        "TPTOP.TPC.RFIR";
        scomaddr    0x01040001;
        capture     group default;
        capture     group FirRegs;
    };

    register TP_CHIPLET_FIR_MASK
    {
        name        "TPTOP.TPC.FIR_MASK";
        scomaddr    0x01040002;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    ############################################################################
    # TP Chiplet LFIR
    ############################################################################

    register TP_LFIR
    {
        name        "TPTOP.TPC.LOCAL_FIR";
        scomaddr    0x0104000a;
        reset       (&, 0x0104000b);
        mask        (|, 0x0104000f);
        capture     group default;
        capture     group FirRegs;
    };

    register TP_LFIR_AND
    {
        name        "TPTOP.TPC.LOCAL_FIR_AND";
        scomaddr    0x0104000b;
        capture     type secondary;
        capture     group never;
    };

    register TP_LFIR_MASK
    {
        name        "TPTOP.TPC.EPS.FIR.LOCAL_FIR_MASK";
        scomaddr    0x0104000d;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    register TP_LFIR_MASK_AND
    {
        name        "TPTOP.TPC.EPS.FIR.LOCAL_FIR_MASK_AND";
        scomaddr    0x0104000e;
        capture     group never;
    };

    register TP_LFIR_MASK_OR
    {
        name        "TPTOP.TPC.EPS.FIR.LOCAL_FIR_MASK_OR";
        scomaddr    0x0104000f;
        capture     group never;
    };

    register TP_LFIR_ACT0
    {
        name        "TPTOP.TPC.EPS.FIR.LOCAL_FIR_ACTION0";
        scomaddr    0x01040010;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    register TP_LFIR_ACT1
    {
        name        "TPTOP.TPC.EPS.FIR.LOCAL_FIR_ACTION1";
        scomaddr    0x01040011;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    ############################################################################
    # Error Report Registers
    ############################################################################

    register TP_ERROR_STATUS
    {
        name        "TPTOP.TPC.ERROR_STATUS";
        scomaddr    0x01030009;
        capture     group default;
        capture     group CerrRegs;
    };

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