path: root/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule

# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule $
#
# IBM CONFIDENTIAL
#
# COPYRIGHT International Business Machines Corp. 2012,2013
#
# p1
#
# Object Code Only (OCO) source materials
# Licensed Internal Code Source Materials
# IBM HostBoot Licensed Internal Code
#
# The source code for this program is not published or otherwise
# divested of its trade secrets, irrespective of what has been
# deposited with the U.S. Copyright Office.
#
# Origin: 30
#
# IBM_PROLOG_END_TAG

    ############################################################################
    # NEST Chiplet Registers
    ############################################################################

    register NEST_CHIPLET_CS_FIR
    {
        name        "TCN.XFIR";
        scomaddr    0x02040000;
        capture     group default;
        capture     group FirRegs;
    };

    register NEST_CHIPLET_RE_FIR
    {
        name        "TCN.RFIR";
        scomaddr    0x02040001;
        capture     group default;
        capture     group FirRegs;
    };

    register NEST_CHIPLET_FIR_MASK
    {
        name        "TCN.FIR_MASK";
        scomaddr    0x02040002;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    ############################################################################
    # NEST Chiplet LFIR
    ############################################################################

    register NEST_LFIR
    {
        name        "TCN.LOCAL_FIR";
        scomaddr    0x0204000a;
        reset       (&, 0x0204000b);
        mask        (|, 0x0204000f);
        capture     group default;
        capture     group FirRegs;
    };

    register NEST_LFIR_MASK
    {
        name        "TCN.EPS.FIR.LOCAL_FIR_MASK";
        scomaddr    0x0204000d;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    register NEST_LFIR_ACT0
    {
        name        "TCN.EPS.FIR.LOCAL_FIR_ACTION0";
        scomaddr    0x02040010;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    register NEST_LFIR_ACT1
    {
        name        "TCN.EPS.FIR.LOCAL_FIR_ACTION1";
        scomaddr    0x02040011;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    ############################################################################
    # NEST Chiplet DMIFIR
    ############################################################################

    register DMIFIR
    {
        name        "DMI.BUSCTL.SCOM.FIR_REG";
        scomaddr    0x02010400;
        reset       (&, 0x02010401);
        mask        (|, 0x02010405);
        capture     group default;
        capture     group FirRegs;
    };

    register DMIFIR_MASK
    {
        name        "DMI.BUSCTL.SCOM.FIR_MASK_REG";
        scomaddr    0x02010403;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    register DMIFIR_ACT0
    {
        name        "DMI.BUSCTL.SCOM.FIR_ACTION0_REG";
        scomaddr    0x02010406;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    register DMIFIR_ACT1
    {
        name        "DMI.BUSCTL.SCOM.FIR_ACTION1_REG";
        scomaddr    0x02010407;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    ############################################################################
    # NEST Chiplet MBIFIR
    ############################################################################

    register MBIFIR
    {
        name        "MBU.MBI.MBI.SCOMFIR.MBIFIRQ";
        scomaddr    0x02010800;
        reset       (&, 0x02010801);
        mask        (|, 0x02010805);
        capture     group default;
        capture     group FirRegs;
    };

    register MBIFIR_MASK
    {
        name        "MBU.MBI.MBI.SCOMFIR.MBIFIRMASK";
        scomaddr    0x02010803;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    register MBIFIR_ACT0
    {
        name        "MBU.MBI.MBI.SCOMFIR.MBIFIRACT0";
        scomaddr    0x02010806;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    register MBIFIR_ACT1
    {
        name        "MBU.MBI.MBI.SCOMFIR.MBIFIRACT1";
        scomaddr    0x02010807;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    ############################################################################
    # NEST Chiplet MBSFIR
    ############################################################################

    register MBSFIR
    {
        name        "MBU.MBS.MBS_FIR_REG";
        scomaddr    0x02011400;
        reset       (&, 0x02011401);
        mask        (|, 0x02011405);
        capture     group default;
        capture     group FirRegs;
    };

    register MBSFIR_MASK
    {
        name        "MBU.MBS.MBS_FIR_MASK_REG";
        scomaddr    0x02011403;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    register MBSFIR_ACT0
    {
        name        "MBU.MBS.MBS_FIR_ACTION0_REG";
        scomaddr    0x02011406;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    register MBSFIR_ACT1
    {
        name        "MBU.MBS.MBS_FIR_ACTION1_REG";
        scomaddr    0x02011407;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    ############################################################################
    # NEST Chiplet MBSECC01FIR
    ############################################################################

    register MBSECC01FIR
    {
        name        "MBU.MBS.ECC01.MBECCFIR";
        scomaddr    0x02011440;
        reset       (&, 0x02011441);
        mask        (|, 0x02011445);
        capture     group default;
        capture     group FirRegs;
    };

    register MBSECC01FIR_AND
    {
        name        "MBU.MBS.ECC01.MBECCFIR_AND";
        scomaddr    0x02011441;
        capture     group never;
    };

    register MBSECC01FIR_MASK
    {
        name        "MBU.MBS.ECC01.MBECCFIR_MASK";
        scomaddr    0x02011443;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    register MBSECC01FIR_ACT0
    {
        name        "MBU.MBS.ECC01.MBECCFIR_ACTION0";
        scomaddr    0x02011446;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    register MBSECC01FIR_ACT1
    {
        name        "MBU.MBS.ECC01.MBECCFIR_ACTION1";
        scomaddr    0x02011447;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    ############################################################################
    # NEST Chiplet MBSECC23FIR
    ############################################################################

    register MBSECC23FIR
    {
        name        "MBU.MBS.ECC23.MBECCFIR";
        scomaddr    0x02011480;
        reset       (&, 0x02011481);
        mask        (|, 0x02011485);
        capture     group default;
        capture     group FirRegs;
    };

    register MBSECC23FIR_AND
    {
        name        "MBU.MBS.ECC23.MBECCFIR_AND";
        scomaddr    0x02011481;
        capture     group never;
    };

    register MBSECC23FIR_MASK
    {
        name        "MBU.MBS.ECC23.MBECCFIR_MASK";
        scomaddr    0x02011483;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    register MBSECC23FIR_ACT0
    {
        name        "MBU.MBS.ECC23.MBECCFIR_ACTION0";
        scomaddr    0x02011486;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    register MBSECC23FIR_ACT1
    {
        name        "MBU.MBS.ECC23.MBECCFIR_ACTION0";
        scomaddr    0x02011487;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    ############################################################################
    # NEST Chiplet MCBIST01FIR
    ############################################################################

    register MCBIST01FIR
    {
        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSFIRQ";
        scomaddr    0x02011600;
        reset       (&, 0x02011601);
        mask        (|, 0x02011605);
        capture     group default;
        capture     group FirRegs;
    };

    register MCBIST01FIR_MASK
    {
        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSFIRMASK";
        scomaddr    0x02011603;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    register MCBIST01FIR_ACT0
    {
        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSFIRACTION0";
        scomaddr    0x02011606;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    register MCBIST01FIR_ACT1
    {
        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSFIRACTION1";
        scomaddr    0x02011607;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    ############################################################################
    # NEST Chiplet MCBIST23FIR
    ############################################################################

    register MCBIST23FIR
    {
        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSFIRQ";
        scomaddr    0x02011700;
        reset       (&, 0x02011701);
        mask        (|, 0x02011705);
        capture     group default;
        capture     group FirRegs;
    };

    register MCBIST23FIR_MASK
    {
        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSFIRMASK";
        scomaddr    0x02011703;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    register MCBIST23FIR_ACT0
    {
        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSFIRACTION0";
        scomaddr    0x02011706;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    register MCBIST23FIR_ACT1
    {
        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSFIRACTION1";
        scomaddr    0x02011707;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    ############################################################################
    # NEST Chiplet NESTFBISTFIR
    ############################################################################

    # FIR not used. Capture for FFDC only.

    register NESTFBISTFIR
    {
        name        "FBIST.FBN.FBN_FIR_REG";
        scomaddr    0x02010880;
        capture     group default;
        capture     group FirRegs;
    };

    ############################################################################
    # NEST Chiplet SCACFIR
    ############################################################################

    register SCACFIR
    {
        name        "SCAC.SCAC_LFIR";
        scomaddr    0x020115c0;
        reset       (&, 0x020115c1);
        mask        (|, 0x020115c5);
        capture     group default;
        capture     group FirRegs;
    };

    register SCACFIR_MASK
    {
        name        "SCAC.SCAC_FIRMASK";
        scomaddr    0x020115c3;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    register SCACFIR_ACT0
    {
        name        "SCAC.SCAC_FIRACTION0";
        scomaddr    0x020115c6;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    register SCACFIR_ACT1
    {
        name        "SCAC.SCAC_FIRACTION1";
        scomaddr    0x020115c7;
        capture     type secondary;
        capture     group default;
        capture     group FirRegs;
    };

    ############################################################################
    # NEST Chiplet MBSSECUREFIR
    ############################################################################

    # This register is hardwired to channel failure (checkstop) and we cannot
    # mask or change the state of the action registers.
    register MBSSECUREFIR
    {
        name        "MBU.MBS.ARB.RXLT.MBSSIRQ";
        scomaddr    0x0201141e;
        reset       (&, 0x0201141f);
        capture     group default;
        capture     group FirRegs;
    };

    ############################################################################
    # Error Report Registers
    ############################################################################

    register NEST_ERROR_STATUS
    {
        name        "TCN.ERROR_STATUS";
        scomaddr    0x02030009;
        capture     group default;
        capture     group CerrRegs;
    };

    register MBIERPT
    {
        name        "MBU.MBI.MBI.MBIERPT0";
        scomaddr    0x0201080F;
        capture     group default;
        capture     group CerrRegs;
    };

    register MBSCERR1
    {
        name        "MBU.MBS.MBSCERR1Q";
        scomaddr    0x02011413;
        capture     group default;
        capture     group CerrRegs;
    };

    register MBSCERR2
    {
        name        "MBU.MBS.MBSCERR2Q";
        scomaddr    0x0201142C;
        capture     group default;
        capture     group CerrRegs;
    };

    register MBSECC01ERRPT_0
    {
        name        "MBU.MBS.ECC01.MBSECCERR0";
        scomaddr    0x02011466;
        capture     group default;
        capture     group CerrRegs;
    };

    register MBSECC01ERRPT_1
    {
        name        "MBU.MBS.ECC01.MBSECCERR1";
        scomaddr    0x02011467;
        capture     group default;
        capture     group CerrRegs;
    };
    register MBSECC23ERRPT_0
    {
        name        "MBU.MBS.ECC23.MBSECCERR0";
        scomaddr    0x020114A6;
        capture     group default;
        capture     group CerrRegs;
    };

    register MBSECC23ERRPT_1
    {
        name        "MBU.MBS.ECC23.MBSECCERR1";
        scomaddr    0x020114A7;
        capture     group default;
        capture     group CerrRegs;
    };

    register MBXERRSTAT_0
    {
        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBXERRSTATQ";
        scomaddr    0x0201168f;
        capture     group default;
        capture     group CerrRegs;
    };

    register MBXERRSTAT_1
    {
        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBXERRSTATQ";
        scomaddr    0x0201178f;
        capture     group default;
        capture     group CerrRegs;
    };

    register SENSORCACHEERRPT
    {
        name        "SCAC.SCAC_ERRRPT";
        scomaddr    0x020115D4;
        capture     group default;
        capture     group CerrRegs;
    };

    ############################################################################
    # Memory ECC Error Address Registers
    ############################################################################

    register MBNCER_0
    {
        name        "MBS Memory NCE Error Address 0 Register";
        scomaddr    0x02011660;
        capture     group default;
    };

    register MBRCER_0
    {
        name        "MBS Memory RCE Error Address 0 Register";
        scomaddr    0x02011661;
        capture     group default;
    };

    register MBMPER_0
    {
        name        "MBS Memory MPE Error Address 0 Register";
        scomaddr    0x02011662;
        capture     group default;
    };

    register MBUER_0
    {
        name        "MBS Memory UE Error Address 0 Register";
        scomaddr    0x02011663;
        capture     group default;
    };

    register MBNCER_1
    {
        name        "MBS Memory NCE Error Address 1 Register";
        scomaddr    0x02011760;
        capture     group default;
    };

    register MBRCER_1
    {
        name        "MBS Memory RCE Error Address 1 Register";
        scomaddr    0x02011761;
        capture     group default;
    };

    register MBMPER_1
    {
        name        "MBS Memory MPE Error Address 1 Register";
        scomaddr    0x02011762;
        capture     group default;
    };

    register MBUER_1
    {
        name        "MBS Memory UE Error Address 1 Register";
        scomaddr    0x02011763;
        capture     group default;
    };

    ############################################################################
    # NEST Chiplet memory scrub/read threshold register
    ############################################################################

    register MBSTR_0
    {
        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSTRQ";
        scomaddr    0x02011655;
        capture     group default;
    };

    register MBSTR_1
    {
        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSTRQ";
        scomaddr    0x02011755;
        capture     group default;
    };