blob: 19362cdf406c246855c7e873dce38ce2cbe2a0cd (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
|
# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_MEM.rule $
#
# IBM CONFIDENTIAL
#
# COPYRIGHT International Business Machines Corp. 2012,2013
#
# p1
#
# Object Code Only (OCO) source materials
# Licensed Internal Code Source Materials
# IBM HostBoot Licensed Internal Code
#
# The source code for this program is not published or otherwise
# divested of its trade secrets, irrespective of what has been
# deposited with the U.S. Copyright Office.
#
# Origin: 30
#
# IBM_PROLOG_END_TAG
############################################################################
# MEM Chiplet Registers
############################################################################
register MEM_CHIPLET_CS_FIR
{
name "TCM.XFIR";
scomaddr 0x03040000;
capture group default;
capture group FirRegs;
};
register MEM_CHIPLET_RE_FIR
{
name "TCM.RFIR";
scomaddr 0x03040001;
capture group default;
capture group FirRegs;
};
register MEM_CHIPLET_FIR_MASK
{
name "TCM.FIR_MASK";
scomaddr 0x03040002;
capture group default;
capture group FirRegs;
};
register MEM_CHIPLET_SPA
{
name "TCM.EPS.FIR.SPATTN";
scomaddr 0x03040004;
capture group default;
capture group FirRegs;
};
register MEM_CHIPLET_SPA_MASK
{
name "TCM.EPS.FIR.SPA_MASK";
scomaddr 0x03040007;
capture group default;
capture group FirRegs;
};
############################################################################
# MEM Chiplet LFIR
############################################################################
register MEM_LFIR
{
name "TCM.LOCAL_FIR";
scomaddr 0x0304000a;
reset (&, 0x0304000b);
mask (|, 0x0304000f);
capture group default;
capture group FirRegs;
};
register MEM_LFIR_MASK
{
name "TCM.EPS.FIR.LOCAL_FIR_MASK";
scomaddr 0x0304000d;
capture group default;
capture group FirRegs;
};
register MEM_LFIR_ACT0
{
name "TCM.EPS.FIR.LOCAL_FIR_ACTION0";
scomaddr 0x03040010;
capture type secondary;
capture group default;
capture group FirRegs;
};
register MEM_LFIR_ACT1
{
name "TCM.EPS.FIR.LOCAL_FIR_ACTION1";
scomaddr 0x03040011;
capture type secondary;
capture group default;
capture group FirRegs;
};
############################################################################
# MEM Chiplet MEMFBISTFIR
############################################################################
# FIR not used. Capture for FFDC only.
register MEMFBISTFIR
{
name "FBIST.FBM.FBM_FIR_REG";
scomaddr 0x03010480;
capture group default;
capture group FirRegs;
};
############################################################################
# Error Report Registers
############################################################################
register MEM_ERROR_STATUS
{
name "TCM.ERROR_STATUS";
scomaddr 0x03030009;
capture group default;
capture group CerrRegs;
};
|